Patents by Inventor Ouyang Hui

Ouyang Hui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8361855
    Abstract: An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: January 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matt Yeh, Yi-Chen Huang, Fan-Yi Hsu, Ouyang Hui
  • Patent number: 8114721
    Abstract: A method of forming a FinFET device is provided. In one embodiment, a fin is formed on a substrate. A gate structure is formed over the fin, the gate structure having a dielectric layer and a conformal first polysilicon layer formed above the dielectric layer. An etch stop layer is formed above the first polysilicon layer and thereafter a second polysilicon layer is formed above the etch stop layer. The second polysilicon layer and the etch stop layer are removed. A metal layer is formed above the first polysilicon layer. The first polysilicon layer is reacted with the metal layer to silicide the first polysilicon layer. Any un-reacted metal layer is thereafter removed and source and drain regions are formed on opposite sides of the fin.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: February 14, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shun Wu Lin, Peng-Soon Lim, Matt Yeh, Ouyang Hui
  • Publication number: 20120018817
    Abstract: An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.
    Type: Application
    Filed: October 4, 2011
    Publication date: January 26, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Matt YEH, Yi-Chen HUANG, Fan-Yi HSU, Ouyang HUI
  • Patent number: 8048733
    Abstract: An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: November 1, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matt Yeh, Yi-Chen Huang, Fan-Yi Hsu, Ouyang Hui
  • Publication number: 20110143510
    Abstract: A method of forming a FinFET device is provided. In one embodiment, a fin is formed on a substrate. A gate structure is formed over the fin, the gate structure having a dielectric layer and a conformal first polysilicon layer formed above the dielectric layer. An etch stop layer is formed above the first polysilicon layer and thereafter a second polysilicon layer is formed above the etch stop layer. The second polysilicon layer and the etch stop layer are removed. A metal layer is formed above the first polysilicon layer. The first polysilicon layer is reacted with the metal layer to silicide the first polysilicon layer. Any un-reacted metal layer is thereafter removed and source and drain regions are formed on opposite sides of the fin.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 16, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shun Wu LIN, Peng-Soon Lim, Matt Yeh, Ouyang Hui
  • Publication number: 20110086502
    Abstract: An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.
    Type: Application
    Filed: April 9, 2010
    Publication date: April 14, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Matt YEH, Yi-Chen HUANG, Fan-Yi HSU, Ouyang HUI