Patents by Inventor Oved Oz
Oved Oz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230266881Abstract: An apparatus includes a memory controller and scrambling circuitry. The memory controller is configured to control a Dynamic Random-Access Memory (DRAM). The scrambling circuitry is configured to maintain one or more scrambling keys associated with one or more active rows of the DRAM, respectively, to identify a memory-access command, which is transferred between the memory controller and the DRAM and which addresses a given active row of the DRAM, and to apply to the command a scrambling key that is associated with the given active row.Type: ApplicationFiled: January 2, 2023Publication date: August 24, 2023Inventors: Joram Peer, Uri Trichter, Oved Oz, Avraham Fishman
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Publication number: 20080273113Abstract: Apparatus for display processing includes a host interface, which is arranged to accept graphical information from a first computer. A first display head is arranged to produce a first digital video signal including first frames representing the graphical information at a first frame rate, for displaying the graphical information on a local display of the first computer. A second display head is arranged to produce a second digital video signal including second frames representing the graphical information at a second frame rate that is lower than the first frame rate. A video redirection module is arranged to regulate a transmission rate of the second digital video signal from the second display head, to capture the second frames that are generated by the second display head and to forward the captured frames to a second computer.Type: ApplicationFiled: May 2, 2007Publication date: November 6, 2008Inventors: Yoel Hayon, Oved Oz, Joram Peer, Uri Trichter
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Patent number: 6771087Abstract: Verification testing of modules packaged within an integrated circuit are conducted utilizing I/O ports of the integrated circuit for inputting or outputting incoming and outgoing signals, with three sets of externally controlled, tri-state buffers provided for each module. A first set selectively connects predetermined I/O contacts of each module interconnected to contacts of other modules, a second set selectively connects predetermined I/O contacts of each module to the I/O ports and a common test bus, and a third set applies the last logic state on each I/O contact before isolation by a buffer from the first set. Whenever a module is selected for testing, the current value that appears on each I/O contact that is connected to other modules is stored in its corresponding bus holder, so as to essentially prevent DC leakage currents.Type: GrantFiled: June 4, 2002Date of Patent: August 3, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Oved Oz, Abraham Mizrahi
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Patent number: 5872960Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.Type: GrantFiled: March 27, 1996Date of Patent: February 16, 1999Assignee: National Semiconductor CorporationInventors: Oved Oz, Gideon Intrater, Yachin Afek
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Patent number: 5649208Abstract: The central processing unit of an integrated circuit data processing system includes both means for processing a first non-maskable interrupt (NMI) request received by the data processing system on a first NMI request line and means for processing a second NMI request received by the data processing system on a second NMI request line different from the first NMI request line and within a predefined time period after receipt of the first NMI request. Both. NMI requests are serviced by the data processing system even if the second NMI request is received prior to completion of processing of the first request.Type: GrantFiled: November 3, 1995Date of Patent: July 15, 1997Assignee: National Semiconductor CorporationInventors: Gideon Intrater, Oved Oz, Meir Tsadik
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Patent number: 5638306Abstract: The present invention is directed to various features of an integrated data processing system that includes a general purpose (GP) CPU core for processing data in accordance with a GP instruction set and a digital signal processor (DSP) module for processing data in accordance with command-list code. The DSP module is operable to execute the command-list code independent of and in parallel with execution of the GP instruction set by the CPU core. The system also includes test hook functions for facilitating production testing of the system.Type: GrantFiled: January 5, 1996Date of Patent: June 10, 1997Assignee: National Semiconductor CorporationInventors: Gideon Intrater, Oved Oz, Alberto Sandbank
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Patent number: 5613149Abstract: An integrated circuit structure for use in identifying a value of an analog signal includes a central processing unit that executes instructions to perform data processing operations. The data processing operations include a successive approximation analog-to-dialog conversion operation to provide a digital value based upon an input data signal. A pulse with modulation (PWM) element converts the digital value to a square-wave output signal having a duty cycle corresponding to the digital value. A PWM element is adapted for connection to a low pass filter such that the square-wave output signal is provided as an input to the low pass filter. The low pass filter provides an output analog signal corresponding to the duty cycle of the square-wave output signal. An input port is adapted for connection to an output of a comparator. The comparator receives as inputs the output analog signal the low pass filter and the analog signal.Type: GrantFiled: October 20, 1995Date of Patent: March 18, 1997Assignee: National Semiconductor CorporationInventors: Yachin Afek, Oved Oz, Gideon Intrater
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Patent number: 5603017Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.Type: GrantFiled: September 20, 1994Date of Patent: February 11, 1997Assignee: National Semiconductor CorporationInventors: Gideon Intrater, Oved Oz, Yachin Afek
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Patent number: 5592677Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.Type: GrantFiled: May 19, 1994Date of Patent: January 7, 1997Assignee: National Semiconductor CorporationInventors: Amos Intrater, Andy Birenbaum, Gideon Intrater, Iddo Carmon, Ilan Shimony, Itael Fraenkel, Lev Epstein, Lior Katzri, Omri Viner, Raya Levitan, Ronny Cohen, Sidi Yomtov, Yehezkel Tzadik, Zvi Greenfeld, Israel Greiss, Oved Oz, Yachin Afek, Meir Tsadik, Moshe Doron, Alberto Sandbank
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Patent number: 5590357Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The OP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.Type: GrantFiled: September 6, 1994Date of Patent: December 31, 1996Assignee: National Semiconductor CorporationInventors: Amos Intrater, Andy Birenbaum, Gideon Intrater, Iddo Carmon, Ilan Shimony, Itael Fraenkel, Lev Epstein, Lior Katzri, Omri Viner, Raya Levitan, Ronny Cohen, Sidi Yomtov, Yehezkel Tzadik, Zvi Greenfeld, Israel Greiss, Oved Oz, Yachin Afek, Meir Tsadik, Moshe Doron, Alberto Sandbank
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Patent number: 5491828Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.Type: GrantFiled: September 16, 1994Date of Patent: February 13, 1996Assignee: National Semiconductor CorporationInventors: Gideon Intrater, Oved Oz, Yachin Afek
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Patent number: 5249286Abstract: A microprocessor architecture that includes capabilities for locking individual entries into its integrated instruction cache and data cache while leaving the remainder of the cache unlocked and available for use in capturing the microprocessor's dynamic locality of reference. The microprocessor also includes the capability for locking instruction cache entries without requiring that the instructions be executed during the locking process.Type: GrantFiled: November 24, 1992Date of Patent: September 28, 1993Assignee: National Semiconductor CorporationInventors: Donald B. Alpert, Oved Oz, Gideon Intrater, Reuven Marko, Alon Shacham