Patents by Inventor Padmaraj Sanjeevarao
Padmaraj Sanjeevarao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11742012Abstract: A memory includes read circuitry for reading values stored in memory cells. The read circuitry includes flipped voltage followers for providing bias voltages to nodes of current paths coupled to sense amplifiers during memory read operations.Type: GrantFiled: May 28, 2021Date of Patent: August 29, 2023Assignee: NXP USA, INC.Inventors: Karthik Ramanan, Jon Scott Choy, Padmaraj Sanjeevarao
-
Patent number: 11521692Abstract: A memory includes a plurality of one-time programmable (OTP) memory cells, wherein each OTP memory cell includes a corresponding storage element capable of being in a permanently blown state or non-blown state. In the non-blown state, the corresponding storage element is capable of being in a low conductive state (LCS) or high conductive state (HCS). Control circuitry is configured to, in response to a received read request having a corresponding access address which selects a set of OTP memory cells, direct write circuitry to apply a voltage differential across the corresponding storage element of each selected OTP memory cell sufficient to set the corresponding storage element to a predetermined one of the LCS or HCS, and, after the write circuitry applies the voltage differential across the corresponding storage element, direct read circuitry to read the selected OTP memory cells to output read data stored in the selected OTP memory cells.Type: GrantFiled: March 18, 2021Date of Patent: December 6, 2022Assignee: NXP USA, Inc.Inventors: Jon Scott Choy, Jacob T. Williams, Karthik Ramanan, Padmaraj Sanjeevarao, Maurits Mario Nicolaas Storms
-
Publication number: 20220383925Abstract: A memory includes read circuitry for reading values stored in memory cells. The read circuitry includes flipped voltage followers for providing bias voltages to nodes of current paths coupled to sense amplifiers during memory read operations.Type: ApplicationFiled: May 28, 2021Publication date: December 1, 2022Inventors: Karthik Ramanan, Jon Scott Choy, Padmaraj Sanjeevarao
-
Publication number: 20220301647Abstract: A memory includes a plurality of one-time programmable (OTP) memory cells, wherein each OTP memory cell includes a corresponding storage element capable of being in a permanently blown state or non-blown state. In the non-blown state, the corresponding storage element is capable of being in a low conductive state (LCS) or high conductive state (HCS). Control circuitry is configured to, in response to a received read request having a corresponding access address which selects a set of OTP memory cells, direct write circuitry to apply a voltage differential across the corresponding storage element of each selected OTP memory cell sufficient to set the corresponding storage element to a predetermined one of the LCS or HCS, and, after the write circuitry applies the voltage differential across the corresponding storage element, direct read circuity to read the selected OTP memory cells to output read data stored in the selected OTP memory cells.Type: ApplicationFiled: March 18, 2021Publication date: September 22, 2022Inventors: Jon Scott Choy, Jacob T. Williams, Karthik Ramanan, Padmaraj Sanjeevarao, Maurits Mario Nicolaas Storms
-
Patent number: 11328784Abstract: A memory includes memory cells having two select transistors per cell. Each of the two select transistors are coupled to two different word lines with each word line being controlled by a separate addressable word line driver circuit. In some embodiments, providing two different word lines from two different word line drivers may provide for a memory where the word lines can apply different voltages based on the memory operation being performed.Type: GrantFiled: September 25, 2020Date of Patent: May 10, 2022Assignee: NXP USA, INC.Inventors: Padmaraj Sanjeevarao, Jon Scott Choy
-
Publication number: 20220101934Abstract: A memory includes memory cells having two select transistors per cell. Each of the two select transistors are coupled to two different word lines with each word line being controlled by a separate addressable word line driver circuit. In some embodiments, providing two different word lines from two different word line drivers may provide for a memory where the word lines can apply different voltages based on the memory operation being performed.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Inventors: Padmaraj Sanjeevarao, Jon Scott Choy
-
Publication number: 20220101903Abstract: A non-volatile memory includes virtual ground circuitry configured to generate a virtual ground voltage at a virtual ground node, a memory array of memory cells in which each memory cell includes a select transistor and a storage element and is coupled to a first column line of a plurality of first column lines; and a first decoder configured to select a set of first column lines for a memory write operation to a selected set of the memory cells. The non-volatile memory also includes write circuitry configured to receive a write value for storage into the selected set of memory cells, and a first column line multiplexer configured to, during the memory write operation, couple each selected first column line of the set of first column lines to the write circuitry, and couple each unselected first column line of the plurality of first column lines to the virtual ground node.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Inventors: Jon Scott Choy, Karthik Ramanan, Padmaraj Sanjeevarao, Jacob T. Williams
-
Patent number: 11289144Abstract: A non-volatile memory includes virtual ground circuitry configured to generate a virtual ground voltage at a virtual ground node, a memory array of memory cells in which each memory cell includes a select transistor and a storage element and is coupled to a first column line of a plurality of first column lines; and a first decoder configured to select a set of first column lines for a memory write operation to a selected set of the memory cells. The non-volatile memory also includes write circuitry configured to receive a write value for storage into the selected set of memory cells, and a first column line multiplexer configured to, during the memory write operation, couple each selected first column line of the set of first column lines to the write circuitry, and couple each unselected first column line of the plurality of first column lines to the virtual ground node.Type: GrantFiled: September 25, 2020Date of Patent: March 29, 2022Assignee: NXP USA, Inc.Inventors: Jon Scott Choy, Karthik Ramanan, Padmaraj Sanjeevarao, Jacob T. Williams
-
Patent number: 11250898Abstract: As disclosed herein, a memory includes an array of resistive memory cells and a voltage regulator circuit that provides a regulated voltage based on a circuit with a replica resistive storage element. The regulated voltage is applied to a mux transistor of a multiplexer of a column decoder that is used to select a particular column line of a memory array from a set of column lines to provide the proper voltage to the memory cell during a write operation to the memory cell.Type: GrantFiled: April 10, 2020Date of Patent: February 15, 2022Assignee: NXP USA, INC.Inventors: Padmaraj Sanjeevarao, Jacob T. Williams, Karthik Ramanan, Jon Scott Choy
-
Patent number: 11170849Abstract: A memory includes a plurality of word line drivers with each driver controlling the voltage of a word line and the voltage of a select line during a memory operation. The driver operates to couple the select line to a first voltage setting terminal when the word line is asserted and couple the select line to a second voltage setting terminal when the word line is not asserted.Type: GrantFiled: September 17, 2020Date of Patent: November 9, 2021Assignee: NXP USA, INC.Inventors: Jon Scott Choy, Padmaraj Sanjeevarao, Jacob T. Williams
-
Publication number: 20210319819Abstract: As disclosed herein, a memory includes an array of resistive memory cells and a voltage regulator circuit that provides a regulated voltage based on a circuit with a replica resistive storage element. The regulated voltage is applied to a mux transistor of a multiplexer of a column decoder that is used to select a particular column line of a memory array from a set of column lines to provide the proper voltage to the memory cell during a write operation to the memory cell.Type: ApplicationFiled: April 10, 2020Publication date: October 14, 2021Inventors: Padmaraj Sanjeevarao, Jacob T. Williams, Karthik Ramanan, Jon Scott Choy
-
Patent number: 11049539Abstract: A magnetoresistive random access memory (MRAM) array has a corresponding MRAM cell, including a Magnetic Tunnel Junction (MTJ), at an intersection of each row and column. A first row of the array is configured as a single one-time-programmable (OTP) row, wherein a first MRAM cell in a first column is connected to a second MRAM cell in a second column. A first MTJ of the first MRAM cell is connected to a first bit line of the first column, and a second MTJ of the second MRAM cell is not connected to a second bit line of the second column. During a write to the first MRAM cell, write circuitry is configured to connect the first and second bit lines and the corresponding source lines such that the select transistors in the first and second MRAM cells are connected in parallel to drive a write current through the first MTJ.Type: GrantFiled: April 29, 2020Date of Patent: June 29, 2021Assignee: NXP USA, Inc.Inventors: Padmaraj Sanjeevarao, Jon Scott Choy, Anirban Roy
-
Patent number: 10573364Abstract: Embodiments of a magnetoresistive random access memory (MRAM) diagnostic system are provided, which includes: preconditioning all bit cells in an MRAM cell array to a data value of one during a diagnostic mode, wherein the MRAM cell array is implemented in an active side of a semiconductor substrate; applying a first magnetic disturb field having a predetermined field strength to the MRAM cell array, subsequent to the preconditioning, wherein the first magnetic disturb field is generated by an antenna implemented in a number of layers of conductive and dielectric material over the active side of the semiconductor substrate; performing a first error correcting code (ECC) read operation to read the MRAM cell array, subsequent to the applying the first magnetic disturb field; and in response to detecting at least one uncorrectable read during the first ECC read operation, setting a fail state and exiting the diagnostic mode.Type: GrantFiled: December 13, 2018Date of Patent: February 25, 2020Assignee: NXP USA, Inc.Inventors: Padmaraj Sanjeevarao, Richard Eguchi, Anirban Roy
-
Patent number: 9396780Abstract: A memory system has a decoder circuit that includes a first driver circuit having an input coupled to receive a first pre-decode signal. The first driver circuit includes transistors wherein a first current electrode of a first transistor is coupled to receive a second pre-decode signal. The decoder circuit includes a second driver circuit having an input coupled to receive a third pre-decode signal. The second driver circuit includes transistors wherein a first current electrode of a third transistor in the stack is coupled to receive the second pre-decode signal. A fifth transistor has a first current electrode coupled to an output of the first driver circuit, a second current electrode coupled to an output of the second driver circuit, and a control electrode coupled to a fourth pre-decode signal.Type: GrantFiled: September 22, 2015Date of Patent: July 19, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Padmaraj Sanjeevarao, David W. Chrudimsky
-
Patent number: 8913436Abstract: A word line driver that includes a pull up transistor for biasing a node of a stack of transistors that are located between a high supply voltage terminal and a low supply voltage terminal. The node is biased at a voltage that is between the high supply voltage and the low supply voltage. The stack of transistors includes a stack of decode transistors and a cascode transistor. The cascode transistor is located between the node and a second node of the stack that is coupled to an inverting circuit.Type: GrantFiled: March 14, 2013Date of Patent: December 16, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Padmaraj Sanjeevarao, David W. Chrudimsky
-
Publication number: 20140269140Abstract: A word line driver that includes a pull up transistor for biasing a node of a stack of transistors that are located between a high supply voltage terminal and a low supply voltage terminal. The node is biased at a voltage that is between the high supply voltage and the low supply voltage. The stack of transistors includes a stack of decode transistors and a cascode transistor. The cascode transistor is located between the node and a second node of the stack that is coupled to an inverting circuit.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Inventors: PADMARAJ SANJEEVARAO, DAVID W. CHRUDIMSKY
-
Patent number: 8737137Abstract: A memory device includes a word line driver circuit, a write voltage generator for providing a write voltage to the word line driver during a write operation to memory cells coupled to the word line driver circuit, and a write bias generator including an output node for providing a write bias voltage that is different from the write voltage to the word line driver circuit during a write operation to memory cells coupled to the word line driver circuit. The write bias voltage is used to reduce current drawn by the word line driver circuit from the write voltage generator during a write operation to memory cells coupled to the word line driver circuit.Type: GrantFiled: January 22, 2013Date of Patent: May 27, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Jon S. Choy, Padmaraj Sanjeevarao
-
Patent number: 8625365Abstract: A memory module decodes an address to determine a one or more wordline select pattern, or other spatial select pattern. An encoder determines an encoded value based upon the wordline select pattern that is compared to an expected encode value. The encode value has fewer than twice the number of address bits used to determine the wordline select pattern.Type: GrantFiled: August 18, 2011Date of Patent: January 7, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Padmaraj Sanjeevarao, David W. Chrudimsky
-
Publication number: 20130044558Abstract: A memory module decodes an address to determine a one or more wordline select pattern, or other spatial select pattern. An encoder determines an encoded value based upon the wordline select pattern that is compared to an expected encode value. The encode value has fewer than twice the number of address bits used to determine the wordline select pattern.Type: ApplicationFiled: August 18, 2011Publication date: February 21, 2013Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Padmaraj Sanjeevarao, David W. Chrudimsky
-
Patent number: 7733126Abstract: A first logic state is at a first output voltage level at a first output of a level shifter that selects a first negative regulation voltage level in response to the first logic state. A negative supply voltage begins at first potential and decreases to the first negative regulation voltage level. The first output voltage level decreases as the negative supply voltage decreases. The first output of the level shifter is switched from the first logic state to a second logic state in response to the negative supply voltage reaching the first negative regulation voltage level. The second logic state is provided at a second output voltage level that selects a second negative regulation voltage level for the negative regulation voltage. The first output of the level shifter remains at the second logic state but is reduced in voltage.Type: GrantFiled: March 31, 2009Date of Patent: June 8, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Jon Choy, David W. Chrudimsky, Padmaraj Sanjeevarao