Patents by Inventor Pai-Yi Chang

Pai-Yi Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10672461
    Abstract: A negative bit line write assist system includes an array voltage supply and a static random access memory (SRAM) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the SRAM cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation. A negative bit line write assist method is also provided.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: June 2, 2020
    Assignee: Nvidia Corporation
    Inventors: Haiyan Gong, Lei Wang, Sing-Rong Li, Hwong-Kwo Lin, Pai-Yi Chang
  • Patent number: 9355710
    Abstract: A hybrid write-assist memory system includes an array voltage supply and a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation. Also, the hybrid write-assist memory system includes a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation. A method of operating a hybrid write-assist memory system is also provided.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: May 31, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Haiyan Gong, Lei Wang, Sing-Rong Li, Hwong-Kwo Lin, Pai-Yi Chang
  • Publication number: 20150206577
    Abstract: A hybrid write-assist memory system includes an array voltage supply and a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation. Also, the hybrid write-assist memory system includes a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation. A method of operating a hybrid write-assist memory system is also provided.
    Type: Application
    Filed: January 23, 2014
    Publication date: July 23, 2015
    Applicant: Nvidia Corporation
    Inventors: Haiyan Gong, Lei Wang, Sing-Rong Li, Hwong-Kwo Lin, Pai-Yi Chang
  • Publication number: 20150206576
    Abstract: A negative bit line write assist system includes an array voltage supply and a static random access memory (SRAM) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the SRAM cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation. A negative bit line write assist method is also provided.
    Type: Application
    Filed: January 22, 2014
    Publication date: July 23, 2015
    Applicant: Nvidia Corporation
    Inventors: Haiyan Gong, Lei Wang, Sing-Rong Li, Hwong-Kwo Lin, Pai-Yi Chang