Abstract: A system for processing signals includes a single integrated circuit chip that includes one or more circuits, the one or more circuits including a first receiver demodulator and a second receiver demodulator. The one or more circuits are operable to: control access to information received by one or both of the first demodulator and/or the second receiver demodulator utilizing at least one secure key stored in on-chip memory within the single integrated circuit chip; and generate an audio stream and a video stream based on one or both of the information received by the first receiver demodulator and/or the information received by the second receiver demodulator. The one or more circuits include one or more video decoders, one or more video and graphics display engines coupled to the one or more video decoders; and one or more video encoders coupled to the one or more video and graphics display engines.

Abstract: Systems and methods that provide a one-time programmable (OTP) memory with fault tolerance are provided. In one example, the OTM memory may include a data portion and a multistage programming (MSP) portion. The data of the data portion may be protected by error coding. The MSP portion may include at least one MSP bit and at least one respective redundant MSP bit.

Abstract: A system for processing signals includes a single integrated circuit chip that includes one or more circuits, the one or more circuits including a first receiver demodulator and a second receiver demodulator. The one or more circuits are operable to: control access to information received by one or both of the first demodulator and/or the second receiver demodulator utilizing at least one secure key stored in on-chip memory within the single integrated circuit chip; and generate an audio stream and a video stream based on one or both of the information received by the first receiver demodulator and/or the information received by the second receiver demodulator. The one or more circuits include one or more video decoders, one or more video and graphics display engines coupled to the one or more video decoders; and one or more video encoders coupled to the one or more video and graphics display engines.

Abstract: A system for an integrated set-top box may include a single integrated circuit chip (SICC). The SICC may include a first satellite receiver demodulator, at least a second satellite receiver demodulator and at least one processor, all integrated within the SICC. The at least one processor may be coupled to the first satellite receiver demodulator and the second satellite receiver demodulator. The at least one processor may generate separate encoded audio and video streams based on at least one demodulated signal received from the first satellite receiver demodulator and/or the at least the second satellite receiver demodulator. The at least one processor may include a MIPS processor, a floating point processor and/or at least one data transport processor. The system may also include a programmable memory integrated within the SICC.

Abstract: A system for processing signals is disclosed and may include a single integrated circuit chip. The single integrated circuit chip (SICC) may include one or more processors coupled to a first satellite receiver demodulator and a second satellite receiver demodulator. The SICC may also include one or more video decoders coupled to the one or more processors, and one or more video and graphics display engines coupled to the one or more video decoders. The SICC may further include one or more video encoders coupled to the one or more video and graphics display engines. One or more video digital-to-analog converters and one or more RF modulators may be integrated within the SICC, and the one or more video digital-to-analog converters and the one or more RF modulators may be coupled to the one or more video encoders. The video decoder may include a standard definition MPEG-2 video decoder.

Abstract: A system for an integrated set-top box may include a single integrated circuit chip (SICC). The SICC may include a first satellite receiver demodulator, at least a second satellite receiver demodulator and at least one processor, all integrated within the SICC. The at least one processor may be coupled to the first satellite receiver demodulator and the second satellite receiver demodulator. The at least one processor may generate separate encoded audio and video streams based on at least one demodulated signal received from the first satellite receiver demodulator and/or the at least the second satellite receiver demodulator. The at least one processor may include a MIPS processor, a floating point processor and/or at least one data transport processor. The system may also include a programmable memory integrated within the SICC.

Abstract: A system for processing signals is disclosed and may include a single integrated circuit chip. The single integrated circuit chip (SICC) may include one or more processors coupled to a first satellite receiver demodulator and a second satellite receiver demodulator. The SICC may also include one or more video decoders coupled to the one or more processors, and one or more video and graphics display engines coupled to the one or more video decoders. The SICC may further include one or more video encoders coupled to the one or more video and graphics display engines. One or more video digital-to-analog converters and one or more RF modulators may be integrated within the SICC, and the one or more video digital-to-analog converters and the one or more RF modulators may be coupled to the one or more video encoders. The video decoder may include a standard definition MPEG-2 video decoder.

Abstract: Certain embodiments of the invention may be found in an single chip satellite set-top box solution that comprises demodulation, decoding and audio/video display functions integrated within a single chip. The single chip solution for the satellite set-top box is adapted to provide demodulation, display, and other related set-top box functions for a system that may be adapted to handle two incoming data streams modulated using an 8 PSK, 8 PSK-turbo or QPSK scheme, for example. Accordingly, the single chip satellite set-top box solution comprise dual 8 PSK/8 PSK-turbo/QPSK demodulators, a MIPS CPU, a 16-bit DDR-SDRAM, graphics display capability for handling two channels, and audio/video decoders and DACs for handling two incoming channels. The single chip satellite set-top box solution may also comprise integrated peripheral support for major set top box functions including a smart card interface, IR receivers, and general purpose input/output (GP/IO) pins.

Abstract: Systems and methods that provide a one-time programmable (OTP) memory with fault tolerance are provided. In one example, the OTM memory may include a data portion and a multistage programming (MSP) portion. The data of the data portion may be protected by error coding. The MSP portion may include at least one MSP bit and at least one respective redundant MSP bit.

Abstract: Systems and methods that provide a one-time programmable (OTP) memory with fault tolerance are provided. In one example, the OTM memory may include a data portion and a multistage programming (MSP) portion. The data of the data portion may be protected by error coding. The MSP portion may include at least one MSP bit and at least one respective redundant MSP bit.

Abstract: Certain embodiments of the invention may be found in an single chip satellite set-top box solution that comprises demodulation, decoding and audio/video display functions integrated within a single chip. The single chip solution for the satellite set-top box is adapted to provide demodulation, display, and other related set-top box functions for a system that may be adapted to handle two incoming data streams modulated using an 8PSK, 8PSK-turbo or QPSK scheme, for example. Accordingly, the single chip satellite set-top box solution comprise dual 8 PSK/8 PSK-turbo/QPSK demodulators, a MIPS CPU, a 16-bit DDR-SDRAM, graphics display capability for handling two channels, and audio/video decoders and DACs for handling two incoming channels. The single chip satellite set-top box solution may also comprise integrated peripheral support for major set top box functions including a smart card interface, IR receivers, and general purpose input/output (GP/IO) pins.

Abstract: Systems and methods that provide a one-time programmable (OTP) memory with fault tolerance are provided. In one example, the OTM memory may include a data portion and a multistage programming (MSP) portion. The data of the data portion may be protected by error coding. The MSP portion may include at least one MSP bit and at least one respective redundant MSP bit.