Patents by Inventor Pallab Chatterjee

Pallab Chatterjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190197605
    Abstract: Systems and methods for processing queries against a large database of transactions. An initial query is processed by a lead analysis engine, but processing does not stop there; the output of the lead analysis engine is used to provide general context, and is also used to select a further-processing module. Multiple results, from multiple further-processing modules, are displayed in a ranked list (or equivalent). The availability of multiple directions of further analysis helps the user to develop an intuition for what trends and drivers might be behind the numbers. Most preferably the resulting information is used to select one or more objects in an immersive environment. The object(s) so selected are visually emphasized, and displayed to the user along with other query results. Optionally, some analysis modules not only process transaction records, but also process customer data (or other exogenous non-transactional data) for use in combination with the transactional data.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 27, 2019
    Applicant: Symphony RetailAI
    Inventors: Stuart Sadler, Ayaz Ali, Aabhas Chandra, Withiel Cole, Andrew Harris, Vishal Kirpalani, Ernesto Laval, Tristan Maw, Stephanie Seiermann, Pallab Chatterjee
  • Publication number: 20150371303
    Abstract: The present application provides new omni-channel marketing capabilities for merchants having physical store locations. When a customer walks up to the physical location, the salespeople are alerted to the customer's presence, and are given information on the customer's preferences—IF the customer has chosen to make that information available to this merchant, or to merchants of this kind. The nearest or most suitable salespeople are cued with the customer's picture and first name, and given information such as sizes, shopping purpose, and general preferences. This permits personalized service interactions to be launched very quickly, and can rapidly build high customer loyalty. The system architecture allows the customer to retain control over her own personal information, and thereby makes it safer for customers to share that information on a limited basis. Tying information to physical locations and authorized merchant users avoids many paths to leakage of personal information.
    Type: Application
    Filed: June 17, 2015
    Publication date: December 24, 2015
    Inventors: Gurvendra S. Suri, Samuel J. Sliman, Pallab Chatterjee
  • Publication number: 20050021541
    Abstract: In one embodiment, a system is provided for managing a centrally managed master repository for core enterprise reference data associated with an enterprise. A centralized master repository contains the reference data, the reference data being associated with multiple schemas, each schema including one or more data models for reference data, each data model including one or more fields. A data management services framework coupled to the repository provides services for managing the reference data in the repository. The services framework supports a master schema including a union of multiple models and associated fields in the multiple schemas. The services framework also supports a thesaurus including, for each field in the master schema, a set of synonyms each representing a mapping between the field in the master schema and a corresponding field in a particular one of the multiple schemas.
    Type: Application
    Filed: May 7, 2004
    Publication date: January 27, 2005
    Inventors: Vasudev Rangadass, Pallab Chatterjee
  • Patent number: 4545034
    Abstract: A transversly injected quasi-floating gate memory cell. A memory transistor in bulk silicon has a channel region in bulk silicon which is capacitatively coupled both to a thin polysilicon quasi-floating gate and to an overlying word line. The thin polysilicon level which comprises the floating gate is not coterminous with the channel region of the memory transistor, but the quasi-floating gate portion of the thin polysilicon layer is connected, through a polysilicon channel region, to a write bit line. The overlying word line thus addresses both the write transistor in a thin polysilicon level and also the memory transistor itself in the substrate.
    Type: Grant
    Filed: June 17, 1983
    Date of Patent: October 1, 1985
    Assignee: Texas Instruments Incorporated
    Inventors: Pallab Chatterjee, Hisashi Shichijo, John E. Leiss