Abstract: A system for a continuous time noise shaping analog-to-digital converter (“ADC”) with a suppressed carrier pulse width modulated (“PWM”) quantizer is disclosed. In particular, a suppressed carrier feedback signal may expand the dynamic range of a sigma delta modulated ADC and enhance the stability of the noise shaping loop.

Abstract: A method and apparatus of converting a data signal in a digital rate converter including upsampling the input data signal at an input sampling rate to an intermediate data signal at an intermediate sampling rate, where the intermediate data signal sample values are stored in a buffer. A plurality of buffer position values are provided from a subset of buffer positions of the buffer to an interpolator, the subset of buffer positions being dependent upon a position indicator. An output data signal is provided by the interpolator at an output sampling rate, where the value of the output data signal is dependent upon a fractional indicator provided to the interpolator. The input sampling rate is based on a first clock signal and the output sampling rate is based on a second clock signal, wherein the first and second clock signal are independent of each other.

Abstract: A system for a continuous time noise shaping analog-to-digital converter (“ADC”) with a suppressed carrier pulse width modulated (“PWM”) quantizer is disclosed. In particular, a suppressed carrier feedback signal may expand the dynamic range of a sigma delta modulated ADC and enhance the stability of the noise shaping loop.

Abstract: A closed loop audio amplifier system and method of powering up/down the system without producing audible artifacts are provided. During power up, a prebias voltage is provided to each output connected to a speaker to increase the voltage to a nominal output level. High impedance switches are then driven at a 50% duty cycle. Feedback from the output is supplied to a servo, which is enabled to fine tune the output voltage. Low impedance switches are then driven at a 50% duty cycle at a quarter cycle timing. The order of the feedback loop depends on which of the high or low impedance switches are driven. The prebias voltage is then removed before audio signals to be amplified are supplied to the system. Timing of driving of the switches is programmable. To power down, essentially the reverse sequence is provided.

Abstract: A closed loop audio amplifier system and method of powering up/down the system without producing audible artifacts are provided. During power up, a prebias voltage is provided to each output connected to a speaker to increase the voltage to a nominal output level. High impedance switches are then driven at a 50% duty cycle. Feedback from the output is supplied to a servo, which is enabled to fine tune the output voltage. Low impedance switches are then driven at a 50% duty cycle at a quarter cycle timing. The order of the feedback loop depends on which of the high or low impedance switches are driven. The prebias voltage is then removed before audio signals to be amplified are supplied to the system. Timing of driving of the switches is programmable. To power down,. essentially the reverse sequence is provided.

Abstract: An audio amplifier includes a digital signal processor (DSP) that contains a noise shaping quantizer having an integrating error amplifier. The integrating error amplifier contains integrators connected in a feedback loop, a summer supplied with an output of each of the integrators, and a saturation function module producing a saturation function. A multiplier is disposed between each pair of adjacent integrators. The multiplier receives a signal from one of the adjacent integrators and the saturation function and supplies a signal to the other of the adjacent integrators. The saturation function decreases the effect of all of the integrators except an integrator to which an input signal to the integrating amplifier is supplied using an input signal to and/or an output signal from the noise shaping quantizer. This permits the duty ratio of the output signal from the noise shaping quantizer to extend from 0% to 100%.

Abstract: An audio amplifier includes a digital signal processor (DSP) that contains a noise shaping quantizer having an integrating error amplifier. The integrating error amplifier contains integrators connected in a feedback loop, a summer supplied with an output of each of the integrators, and a saturation function module producing a saturation function. A multiplier is disposed between each pair of adjacent integrators. The multiplier receives a signal from one of the adjacent integrators and the saturation function and supplies a signal to the other of the adjacent integrators. The saturation function decreases the effect of all of the integrators except an integrator to which an input signal to the integrating amplifier is supplied using an input signal to and/or an output signal from the noise shaping quantizer. This permits the duty ratio of the output signal from the noise shaping quantizer to extend from 0% to 100%.

Abstract: A digital amplifier and method are provided to convert digital base-band signals to a pair of digital switching waveforms switching at a carrier frequency to create a modulated RF signal. The digital amplifier contains variable frequency suppressed carrier PWM generators that produce in-phase and quadrature-phase differential signals, a mixer that combines the differential signals, a decoder that decodes the combined signals, and a power stage that receives signals from the decoder and provides an amplified signal at the carrier frequency using switches. The mixer combines the differential signals such that only one of the differential signals is output in a period. The carrier generators have integral noise shaping and use a random period signal to re-distribute quantization noise to a band outside an RF band of interest and reduce EMI of the RF signal.

Abstract: Systems and methods are described for full bridge integral noise shaping for quantization of pulse width modulated signals. A method for full bridge integral noise shaping comprises: receiving a first and a second reference PWM signal; summing the first and second reference PWM signals with a quantization error correction; quantizing the sum into a first and a second output PWM signal; differentially integrating the first and second reference PWM signals and the first and second output PWM signals according to a full bridge integral noise shaping algorithm to obtain the quantization error correction. An apparatus for performing a full bridge integral noise shaping quantization of a pulse modulated signal, includes: a single-ended to differential conversion circuit; and a full bridge INS quantizer circuit, coupled to the single-ended to differential conversion circuit.

Abstract: A method and apparatus having a digital pulse width modulation generator with integral noise shaping is provided. The apparatus for generating a digital pulse width modulation signal includes a random period signal generator, a noise shaping unit, a duty ratio quantizer, and a PWM counter. The random period signal generator generates a random period signal. The noise shaping unit is responsive to at least a digital signal, the random period signal, and a delayed digital signal for generating a corrected signal. The duty ratio quantizer is responsive to the corrected digital signal, the random period signal, and a quantization clock signal, and generates a first duty ratio signal and a second duty ratio signal. The PWM counter is responsive to the first and second duty ratio signals and a quantization clock signal, and generates positive and negative PWM signals, respectively.

Abstract: A method for providing a current path during switching transitions of a switching circuit while limiting the short circuit current. In one embodiment, a switching circuit includes a passive break-before-make element in series with two switches. An alternate embodiment includes a make-before-break element in parallel with the switches. The passive break-before-make element, or make-before-break element, provides a high impedance in a short term and a low impedance in a long term. The switching circuit may be coupled to a load through a low pass filter. In one embodiment, the switching circuit is used in a switching audio amplifier circuit, where correction of nonlinearities incorporates analog feedback to modify the duty ratio of a digitally generated switching signal in the analog domain.

Abstract: A method and apparatus having a digital pulse width modulation generator with integral noise shaping is provided. The apparatus for generating a digital pulse width modulation signal includes a random period signal generator, a noise shaping unit, a duty ratio quantizer, and a PWM counter. The random period signal generator generates a random period signal. The noise shaping unit is responsive to at least a digital signal, the random period signal, and a delayed digital signal for generating a corrected signal. The duty ratio quantizer is responsive to the corrected digital signal, the random period signal, and a quantization clock signal, and generates a first duty ratio signal and a second duty ratio signal. The PWM counter is responsive to the first and second duty ratio signals and a quantization clock signal, and generates positive and negative PWM signals, respectively.

Abstract: A system and method for analog-to-digital conversion using digital pulse width modulation (PWM) is disclosed. The method and system according to the disclosed invention converts an analog input signal to a digital signal in pulse code modulated (PCM) form. The disclosed invention uses a feedback circuit to perform PWM of the analog input signal. The PWM signal is then decimated to obtain the digital signal in PCM form. The system according to the disclosed invention requires lower operating frequency and dissipates lesser power than prior art systems providing the same sampling frequency and resolution. The operation at a lower frequency is achieved by obtaining two samples from every pulse of the PWM signal; the first sample being obtained from the right duty ratio, and the second sample being obtained form the left duty ratio. Further, the disclosed invention has lesser implementation complexity and higher signal-to-noise ratio than prior art.

Abstract: A system and method for analog-to-digital conversion using digital pulse width modulation (PWM) is disclosed. The method and system according to the disclosed invention converts an analog input signal to a digital signal in pulse code modulated (PCM) form. The disclosed invention uses a feedback circuit to perform PWM of the analog input signal. The PWM signal is then decimated to obtain the digital signal in PCM form. The system according to the disclosed invention requires lower operating frequency and dissipates lesser power than prior art systems providing the same sampling frequency and resolution. The operation at a lower frequency is achieved by obtaining two samples from every pulse of the PWM signal; the first sample being obtained from the right duty ratio, and the second sample being obtained form the left duty ratio. Further, the disclosed invention has lesser implementation complexity and higher signal-to-noise ratio than prior art.

Abstract: Disclosed is a method and/or apparatus for adjusting the sample time and order associated with a digital correction system for maximizing output power and minimizing power stage delay sensitivity of a switching power stage. In certain embodiments, the sample point of an ADC may be changed as a function of the duty ratio of the PWM signal thus allowing higher performance and use of less expensive power stage components. In addition, adjustment of the order of an integrating error amplifier in the system permits operation of the power stage with an output being permitted to saturate up to the power supply rails, thus increasing a power output of the power stage.

Abstract: A method and apparatus of converting a data signal in a digital rate converter including upsampling the input data signal at an input sampling rate to an intermediate data signal at an intermediate sampling rate, where the intermediate data signal sample values are stored in a buffer. A plurality of buffer position values are provided from a subset of buffer positions of the buffer to an interpolator, the subset of buffer positions being dependent upon a position indicator. An output data signal is provided by the interpolator at an output sampling rate, where the value of the output data signal is dependent upon a fractional indicator provided to the interpolator. The input sampling rate is based on a first clock signal and the output sampling rate is based on a second clock signal, wherein the first and second clock signal are independent of each other.

Abstract: Disclosed is a method and/or apparatus for adjusting the sample time and order associated with a digital correction system for maximizing output power and minimizing power stage delay sensitivity of a switching power stage. In certain embodiments, the sample point of an ADC may be changed as a function of the duty ratio of the PWM signal thus allowing higher performance and use of less expensive power stage components. In addition, adjustment of the order of an integrating error amplifier in the system permits operation of the power stage with an output being permitted to saturate up to the power supply rails, thus increasing a power output of the power stage.

Abstract: A power amplifier circuit for receiving a variable envelope input signal and for producing an amplified output signal is provided. The power amplifier circuit includes an envelope approximation circuit, an envelope amplifier circuit, a phasor approximation circuit, a quadrature modulation circuit, and a power amplifier. The envelope approximation circuit receives the variable envelope input signal and produces a bandlimited estimated envelope signal, corresponding to the amplitude of the variable envelope input signal. The bandlimited estimated envelope signal is then amplified by an envelope amplifier circuit. The amplified envelope signal is then coupled to the supply input of the power amplifier. The phasor approximation circuit receives the variable envelope input signal and produces a bandlimited estimated phasor signal. The quadrature modulation circuit receives the estimated phase signal and produces a modulated phase signal.

Abstract: A switching amplifier generates noise at its switching frequency and harmonics thereof. The noise at these harmonics, for an audio amplifier, will be generated with significant amplitude in the AM band. Thus, an AM tuner will experience interference problems if the tuner frequency is sufficiently close to one of these harmonics. To avoid this problem the switching frequency of the switching amplifier is chosen based on the tuner frequency. Thus, the switching frequency is chosen to avoid having harmonics at or too near the chosen tuner frequency. The switching amplifier is disabled when the tuner is in seek or scan mode. Instead of using the tuner frequency to determine what switching frequency should be used to avoid interference, the interference can be detected directly to cause a change in the switching frequency and thus remove the interference.

Abstract: A power amplifier circuit for receiving a variable envelope input signal and for producing an amplified output signal is provided. The power amplifier circuit includes an envelope approximation circuit, an envelope amplifier circuit, a phasor approximation circuit, a quadrature modulation circuit, and a power amplifier. The envelope approximation circuit receives the variable envelope input signal and produces a bandlimited estimated envelope signal, corresponding to the amplitude of the variable envelope input signal. The bandlimited estimated envelope signal is then amplified by an envelope amplifier circuit. The amplified envelope signal is then coupled to the supply input of the power amplifer. The phasor approximation circuit receives the variable envelope input signal and produces a bandlimited estimated phasor signal. The quadrature modulation circuit receives the estimated phase signal and produces a modulated phase signal.