Patents by Inventor Palle Birk
Palle Birk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7649968Abstract: A timing system is disclosed for use in a wireless communication system that includes wireless transceiver and a digital baseband processing system. The timing system includes a primary clock generation system that provides a low frequency clock that is used as the reference clock for a digital signal processing system, which generates low frequency timing signals, and a secondary clock generation system that provides a high frequency clock that is used by the wireless transceiver to produce high resolution timing signals to control the timing of the wireless transceiver. The high resolution timing signals are commenced responsive to a low resolution timing signal.Type: GrantFiled: November 10, 2005Date of Patent: January 19, 2010Assignee: Mediatek Inc.Inventors: Thomas Barber, Aiguo Yan, Palle Birk, Pier Bove
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Patent number: 7454169Abstract: The present invention is directed to methods and apparatus which may be used to help prevent electronic devices, including cell phones, from operating with software copied from (and only authorized for use by or on) another device. A further aspect is a device, including a cell phone, for example, that employs any of such methods and apparatus. Aspects of the present invention compare a program identifier (associated with software stored in a device) to a reference identifier for the device, so as to determine whether the software is authorized for use with that device. Some embodiments respond to the comparison substantially in hardware, so that the software being checked is less able to prevent the device from being disabled in the event that the program identifier and the reference identifier do not match one another.Type: GrantFiled: July 31, 2002Date of Patent: November 18, 2008Assignee: MediaTek Inc.Inventors: Joern Soerensen, Palle Birk, Frederic Boutaud
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Patent number: 7433389Abstract: Methods and apparatus are provided for spread spectrum signal processing in a wireless communication system. The apparatus includes a control processor to generate commands for processing spread spectrum signal components and a reconfigurable coprocessor to process the spread spectrum signal components based on the commands and to provide reports to the control processor based on results of processing the signal components.Type: GrantFiled: November 20, 2002Date of Patent: October 7, 2008Assignee: MediaTek Inc.Inventors: Joern Soerensen, Palle Birk, Zoran Zvonar
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Patent number: 7292649Abstract: A homodyne receiver is provided for receiving GSM and UMTS transmissions. The receiver may also be used for other transmission schemes. The receiver includes an electronically reconfigurable low pass filter and an off set generator for providing DC offset correction for offsets which may be generated as a result of coupling between a local radio frequency oscillator and the receiver front end.Type: GrantFiled: December 30, 2002Date of Patent: November 6, 2007Assignee: Analog Devices, Inc.Inventors: Simon Atkinson, Palle Birk, Stacey Ho, Zoran Zvonar, Aidan Cahalane
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Patent number: 7106805Abstract: A dual mode transmitter for GSM and UMTS operation is provided. The GSM and UMTS paths share an oscillator and an intermediate frequency stage. Also, with the exception of the final stage of power amplification, the transmitter is provided as an integrated device.Type: GrantFiled: December 30, 2002Date of Patent: September 12, 2006Assignee: Analog Devices, Inc.Inventors: Simon Atkinson, Palle Birk, Jonathan Richard Strange
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Publication number: 20060120495Abstract: A timing system is disclosed for use in a wireless communication system that includes wireless transceiver and a digital baseband processing system. The timing system includes a primary clock generation system that provides a low frequency clock that is used as the reference clock for a digital signal processing system, which generates low frequency timing signals, and a secondary clock generation system that provides a high frequency clock that is used by the wireless transceiver to produce high resolution timing signals to control the timing of the wireless transceiver. The high resolution timing signals are commenced responsive to a low resolution timing signal.Type: ApplicationFiled: November 10, 2005Publication date: June 8, 2006Inventors: Thomas Barber, Aiguo Yan, Palle Birk, Pier Bove
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Patent number: 7058364Abstract: A radio transceiver suitable for use in a mobile telephone is provided. The transceiver is operable in dual modes so as to be able to operate with both GSM and UMTS systems. In a preferred embodiment the transmitter section receives base band signals and up-converts them to an intermediate frequency of approximately 450 MHz. This is then mixed with local oscillator frequency of approximately 1.35 GHz, such that a difference frequency allows operation in the GSM 850/950 MHz band, and the sum frequency allows operation in the GSM 1800/1900 MHz bands. The frequency addition allows operation in the UMTS band. The receiver portion of the transceiver comprises a direct conversion receiver for down-converting the received signal without use of an intermediate frequency.Type: GrantFiled: December 30, 2002Date of Patent: June 6, 2006Assignee: Analog Devices, Inc.Inventors: Simon Atkinson, Palle Birk
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Patent number: 6978350Abstract: Methods and apparatus are provided for operating an embedded processor system that includes a processor and a cache memory. The method includes filling one or more lines in the cache memory with data associated with a first task, executing the first task, and, in response to a cache miss during execution of the first task, performing a cache line fill operation and, during the cache line fill operation, executing a second task. The cache memory may notify the processor of the line fill operation by generating a processor interrupt or by notifying a task scheduler running on the processor.Type: GrantFiled: August 29, 2002Date of Patent: December 20, 2005Assignee: Analog Devices, Inc.Inventors: Palle Birk, Joern Soerensen, Michael S. Allen, Jose Fridman
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Patent number: 6950672Abstract: A clock enable system for a multichip device includes a first integrated circuit including a clock signal and at least a second integrated circuit including at least one functional block periodically requiring clock signals from the first integrated circuit; a clock required circuit responsive to each functional block for providing a clock required signal in response to activation of any one or more of the functional blocks; and a clock enable circuit responsive to the clock required signal for enabling the first integrated circuit to provide clock signals to the functional blocks on the second integrated circuit.Type: GrantFiled: May 30, 2002Date of Patent: September 27, 2005Assignee: Analog Devices, Inc.Inventors: Jeffrey C. Gealow, Thomas J. Barber, Jr., Palle Birk, Joern Soerensen
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Patent number: 6895459Abstract: A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.Type: GrantFiled: September 10, 2003Date of Patent: May 17, 2005Assignee: Analog Devices, Inc.Inventors: Rainer R. Hadwiger, Paul D. Krivacek, Jørn Sørensen, Palle Birk
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Patent number: 6889331Abstract: A dynamic power controller is provided that identifies a clock frequency requirement of a processor and determines a voltage requirement to support the clock frequency requirement. The dynamic power controller transitions the processor to a power state defined by the clock frequency requirement and the voltage requirement. In particular, a voltage level indicated by the voltage requirement is supplied to the processor and the frequency distribution indicated by the frequency requirement is provided to the clocks signals of the processor.Type: GrantFiled: August 29, 2002Date of Patent: May 3, 2005Assignee: Analog Devices, Inc.Inventors: Joern Soerensen, Michael Allen, Palle Birk
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Publication number: 20040204003Abstract: The present invention is directed to methods and apparatus which may be used to help prevent electronic devices such as, for example, cell phones from operating with software copied from (and only authorized for use by) another device. The present invention is also directed to devices such as, for example, cell phones, that employ any of such methods and apparatus.Type: ApplicationFiled: July 31, 2002Publication date: October 14, 2004Inventors: Joern Soerensen, Palle Birk, Frederic Boutaud
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Patent number: 6768358Abstract: A PLL frequency multiplier is provided having a latency substantially equal to the wake-up time of the PLL. An operative clock signal is provided to a processor while the PLL is acquiring phase lock by ensuring that the clock signal does not contain frequencies above a target frequency of a PLL and below a predetermined threshold frequency. In particular, a frequency divider and a frequency detector are provided to prevent the frequency of the clock signal from operating outside the range defined by the threshold and target frequencies.Type: GrantFiled: August 29, 2002Date of Patent: July 27, 2004Assignee: Analog Devices, Inc.Inventors: Palle Birk, Joern Soerensen
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Patent number: 6738845Abstract: A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.Type: GrantFiled: November 3, 2000Date of Patent: May 18, 2004Assignee: Analog Devices, Inc.Inventors: Rainer R. Hadwiger, Paul D. Krivacek, Jørn Sørensen, Palle Birk
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Publication number: 20040049293Abstract: A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.Type: ApplicationFiled: September 10, 2003Publication date: March 11, 2004Applicant: Analog Devices, Inc.Inventors: Rainer R. Hadwiger, Paul D. Krivacek, Joern Soerensen, Palle Birk
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Publication number: 20030224745Abstract: A clock enable system for a multichip device includes a first integrated circuit including a clock signal and at least a second integrated circuit including at least one functional block periodically requiring clock signals from the first integrated circuit; a clock required circuit responsive to each functional block for providing a clock required signal in response to activation of any one or more of the functional blocks; and a clock enable circuit responsive to the clock required signal for enabling the first integrated circuit to provide clock signals to the functional blocks on the second integrated circuit.Type: ApplicationFiled: May 30, 2002Publication date: December 4, 2003Inventors: Jeffrey C. Gealow, Thomas J. Barber, Palle Birk, Joern Soerensen
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Publication number: 20030157915Abstract: A homodyne receiver is provided for receiving GSM and UMTS transmissions. The receiver may also be used for other transmission schemes. The receiver includes an electronically reconfigurable low pass filter and an off set generator for providing DC offset correction for offsets which may be generated as a result of coupling between a local radio frequency oscillator and the receiver front end.Type: ApplicationFiled: December 30, 2002Publication date: August 21, 2003Inventors: Simon Atkinson, Palle Birk, Stacy Ho, Zoran Zvonar, Aidan Cahalane
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Publication number: 20030157909Abstract: A dual mode transmitter for GSM and UMTS operation is provided. The GSM and UMTS paths share an oscillator and an intermediate frequency stage. Also, with the exceptio of the final stage of power amplification, the transmitter is provided as an integrated device.Type: ApplicationFiled: December 30, 2002Publication date: August 21, 2003Inventors: Simon Atkinson, Palle Birk, Jonathan Richard Strange
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Publication number: 20030157901Abstract: A dual mode transceiver is provided in which a frequency synthesizer is shared by the transmit and receive channels.Type: ApplicationFiled: December 30, 2002Publication date: August 21, 2003Inventors: Simon Atkinson, Palle Birk
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Publication number: 20030157912Abstract: An automatic gain control is provided for a multi-mode receiver. The gain control includes feed forward controller 402 which sets up an initial gain rapidly based on a measurement of signal strength or upon mode information, and a feedback controller 450 which then takes responsibility for maintaining a signal at a desired amplitude.Type: ApplicationFiled: December 30, 2002Publication date: August 21, 2003Inventors: Simon Atkinson, Palle Birk