Patents by Inventor Pan Wang

Pan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10442976
    Abstract: An oil-soluble coated particle flow modifier, a preparation method thereof, and a use thereof in fractured-vuggy carbonate reservoirs mining. The oil-soluble coated particle flow modifier is of a core-shell structure, which has a core layer of a coated core and a shell layer of a coating agent, wherein the coated core is made of a plugging material, and the coating agent consists of petroleum resin and hollow beads. Based on the total weight of the coated particle flow modifier, the content of the petroleum resin, the hollow beads, the cotton linters, and the coated cores is 10-40 wt %, 9-40 wt %, 1-10 wt %, and 35-80 wt %, respectively. A preparation method of the coated particle flow modifier and a use of the coated particle flow modifier in fractured-vuggy carbonate reservoirs mining to improve oil recovery is also provided.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: October 15, 2019
    Assignees: China University of Geosciences (Beijing), China University of Petroleum (East China)
    Inventors: Qing You, Caili Dai, Long He, Jichao Fang, Baolei Jiao, Liang Li, Guang Zhao, Yifei Liu, Yan Zhang, Pan Wang
  • Publication number: 20190276919
    Abstract: Provided is a method of heat treating a die cast aluminum alloy component. A die cast component has at least one thin walled region with a thickness of ?5 mm. The alloy has silicon at ?6.5 mass % to ?15.5 mass %, copper at ?0.1 mass % to ?3.5 mass %, magnesium at ?0.5 mass %, manganese at ?0.6 mass %, and chromium at ?0.6 mass %. The method includes quenching the die cast component at a cooling rate of ? about 100° C./second to a first temperature of less than 50° C. and age hardening by heating the die cast component to a second temperature of ? about 150° C. for a predetermined duration of time to facilitate formation of particles of Mg2Si in an aluminum alloy matrix. The aluminum alloy treated by the method can form lightweight, high strength, high ductility components.
    Type: Application
    Filed: December 9, 2016
    Publication date: September 12, 2019
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Bin HU, Pan WANG
  • Publication number: 20190229199
    Abstract: Semiconductor devices and methods of forming the same are disclosed. A semiconductor device includes a substrate, a gate structure over the substrate, a spacer and a source/drain region. The gate structure is disposed over the substrate. The spacer is disposed on a sidewall of the gate structure, wherein the spacer has a top surface lower than a top surface of the gate structure. The source/drain region is disposed adjacent to a sidewall of the spacer.
    Type: Application
    Filed: January 23, 2018
    Publication date: July 25, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Tsun Tsai, I-Chih Chen, Chih-Mu Huang, Jiun-Jie Huang, Jen-Pan Wang
  • Publication number: 20190177818
    Abstract: An aluminum-magnesium alloy is disclosed which provides superior properties for casting in steel dies and good ductility for forming castings of complex shapes, including thin-wall portions. The aluminum-based alloy contains, in weight percent, about 2-15 percent magnesium, 0.2 to 3 percent silicon, 0.05 to 0.5 percent chromium, 0.05 to 0.5 percent manganese, 0.05 to 0.2% titanium, and a minimal content of iron. In its molten state this aluminum-magnesium-chromium alloy can be pushed into the molding cavities of iron-based dies in a high pressure die casting procedure and conform to complexly-shaped die surfaces with thin cavity portions without dissolving appreciable amounts of iron or experiencing die soldering on the die surfaces. The resulting castings display good strength and ductility and can be further enhanced by an artificial aging process after solution heat treatment.
    Type: Application
    Filed: June 10, 2016
    Publication date: June 13, 2019
    Inventors: Bin Hu, Pan Wang
  • Publication number: 20190118251
    Abstract: Methods of casting lightweight, high-strength aluminum cast structural components are provided wherein the casting is accomplished by low-pressure die casting or gravity casting. The aluminum cast structural component is preferably composed of an aluminum-based alloy comprising silicon at ?about 4 to ?about 7 wt. %; iron at ?about 0.15 wt. %; manganese at ?about 0.5 wt. %; chromium at ?about 0.15 to ?about 0.5 wt. %; magnesium at ?about 0.8 wt. %; zinc at ?about 0.01 wt. %; titanium at ?about 0.05 to ?about 0.15 wt. %; phosphorus at ?about 0.003 wt. %; strontium at ?about 0.015 wt. % and a balance of aluminum.
    Type: Application
    Filed: April 20, 2016
    Publication date: April 25, 2019
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Bin HU, Pan WANG
  • Patent number: 10266882
    Abstract: Disclosed are a human rare blood type detection method, a kit, a rapid screening method and applications thereof. By using multiple pairs of PCR specific primers directing to the SNP loci of multiple rare blood types, the SNP loci of multiple rare blood types are simultaneously detected in the same PCR reaction system; and the multiplex PCR detection method and a Pool detection method are combined to rapidly screen the human rare blood types.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: April 23, 2019
    Assignee: SHANGHAI BLOOD CENTRE
    Inventors: Luyi Ye, Ziyan Zhu, Zhonghui Guo, Yunlei He, Huanhuan Gao, Pan Wang, Li Xie, Aoxue Zhu, Wei Zhang, Wenjie Gao, Qixiu Yang
  • Patent number: 10256233
    Abstract: A method for forming a semiconductor device and the resulting device are provided. At least one capacitor in a first gate structure is formed over a substrate. The at least one capacitor includes a first gate electrode including a first conductive layer, a semiconductor layer including a semiconductor material and a dopant, a dielectric layer disposed between the first gate electrode and the semiconductor layer, and a second conductive layer contacting the semiconductor layer. The at least one resistor includes a third conductive layer and is electrically connected to the at least one capacitor.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: April 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huan-Kuan Su, Yu-Hong Pan, Jen-Pan Wang, Tong-Min Weng, Tsung-Han Wu
  • Patent number: 10189862
    Abstract: The present invention provides a novel phenothiazine-pyridine compound that is an effective photosensitizer useful for photodynamic therapy. Also provided is a method for inhibiting cell proliferation or for treating a disease involving inappropriate cell proliferation.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: January 29, 2019
    Assignee: The Chinese University of Hong Kong
    Inventors: Chuanshan Xu, Qicai Xiao, Wing Nang Leung, Pan Wang, Hungkay Lee
  • Publication number: 20190024226
    Abstract: A method of manufacturing a pin (46) for a o mold (28) includes forming the pin (46) to include a substantially uniform initial hardness throughout the entire structure of the formed pin (46). The formed pin (46) is then processed with a hardening process, such that the processed pin(46) exhibits a hardness defining a hardness gradient that gradually increases from the initial hardness at a central interior region (56) of the pin (46) to an increased surface hardness at an exterior surface (60) of the pin (46). After processing the pin (46) with the hardening process, a coating (64) maybe deposited onto the exterior surface (60) of the pin (46) with a physical vapor deposition process. The coating (64) exhibits a hardness that is greater than the hardness of the increased surface hardness of the exterior surface (60) of the pin (46). The pin (46) may include, for example, a core pin, a squeeze pin, or an ejector pin.
    Type: Application
    Filed: January 22, 2016
    Publication date: January 24, 2019
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Bin Hu, Pan Wang, Yiwu Xu
  • Publication number: 20180342502
    Abstract: A method for forming a semiconductor device and the resulting device are provided. At least one capacitor in a first gate structure is formed over a substrate. The at least one capacitor includes a first gate electrode including a first conductive layer, a semiconductor layer including a semiconductor material and a dopant, a dielectric layer disposed between the first gate electrode and the semiconductor layer, and a second conductive layer contacting the semiconductor layer. The at least one resistor includes a third conductive layer and is electrically connected to the at least one capacitor.
    Type: Application
    Filed: January 30, 2018
    Publication date: November 29, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huan-Kuan Su, Yu-Hong Pan, Jen-Pan Wang, Tong-Min Weng, Tsung-Han Wu
  • Patent number: 10062603
    Abstract: The present disclosure relates a back-end-of-the-line (BEOL) metallization stack having an air gap disposed between adjacent metal interconnect features, which provides for an inter-level dielectric material with a low dielectric constant. In some embodiments, the BEOL metallization stack has an inter-level dielectric (ILD) layer disposed over a substrate. A metal interconnect layer is disposed within the ILD layer, and an air gap is arranged disposed within the ILD layer at a position between a first feature and a second feature of the metal interconnect layer. The air gap has an upper surface with a first curve that meets a second curve at a peak arranged below a top of the metal interconnect layer. The first curve becomes steeper as a distance from the peak decreases and the second curve becomes steeper as a distance from the peak decreases.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: August 28, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ru-Shang Hsiao, Chih-Fu Chang, Jen-Pan Wang
  • Patent number: 10053985
    Abstract: The invention discloses a real-time water-level monitoring system for a dumping site of an open-pit coal mine. The dumping site of the open-pit coal mine comprises an aboveground part and an underground part, where the aboveground part is a stacking site (1) located above an original ground surface. The real-time water-level monitoring system for a dumping site of an open-pit coal mine comprises a first measuring well (2) and a second measuring well (3), where the first measuring well (2) is arranged vertically in the center of the stacking site (1), and the second measuring well (3) includes a vertical section (301), a horizontal section (302), and a free section (303) connected in sequence; and a first water-impermeable layer (4), a second water-impermeable layer (5), and a third water-impermeable layer (6) are provided internally in the stacking site (1).
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: August 21, 2018
    Assignee: CHINA UNIVERSITY OF MINING & TECHNOLOGY-BEIJING
    Inventors: Suping Peng, Feisheng Feng, Pingjie Fu, Wenfeng Du, Pan Wang
  • Patent number: 10018789
    Abstract: A method and an apparatus for coupling an optical waveguide to a single-mode fiber are disclosed. The apparatus includes a substrate, a first optical waveguide, a single-mode fiber and a second optical waveguide. The first optical waveguide, the single-mode fiber and the second optical waveguide dispose on the substrate. One end of the single-mode fiber has an optical fiber taper structure. One end of the second optical waveguide is optically coupled to the first optical waveguide. Another end of the second optical waveguide is optically coupled to the single-mode fiber using the optical fiber taper structure of the single-mode fiber.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: July 10, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Pan Wang, Can Zhang, Qinfen Hao
  • Patent number: 10008501
    Abstract: The present disclosure relates to a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the transistor device has a source region and a drain region disposed within a semiconductor substrate. A sandwich film stack is laterally positioned between the source region and the drain region. The sandwich film stack has a lower layer, a middle layer of a carbon doped semiconductor material disposed over the lower layer, and an upper layer disposed over the middle layer. A gate structure is disposed over the sandwich film stack. The gate structure is configured to control a flow of charge carriers in a channel region located between the source region and the drain region.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ru-Shang Hsiao, Ling-Sung Wang, Chih-Mu Huang, Cing-Yao Chan, Chun-Ying Wang, Jen-Pan Wang
  • Patent number: 9978744
    Abstract: A passive device and method of fabricating the passive device are disclosed herein. The capacitor structure incorporates a resistor and a capacitor. An exemplary method includes receiving a substrate that has undergone front end of line (FEOL) processing, and performing back end of line (BEOL) processing on the substrate, wherein a capacitor structure is formed over the substrate during the BEOL processing, the capacitor structure incorporating a resistor with a capacitor. The BEOL processing can include performing a first metallization process to form a bottom plate of the capacitor structure; forming a dielectric spacer of the capacitor structure over the bottom plate; forming a top plate of the capacitor structure over the dielectric spacer; and performing a second metallization process to form contacts coupled to the top plate and the bottom plate of the capacitor structure.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Fu Chang, Jen-Pan Wang
  • Publication number: 20180127859
    Abstract: In an example of a method for increasing strength of an aluminum alloy, the aluminum alloy is formed in a molten state. The aluminum alloy includes from about 4 wt % to about 11 wt % silicon, from greater than 0.2 wt % to about 0.5 wt % chromium, from about 0.1 wt % to about 0.5 wt % magnesium, from about 0.01 wt % to about 0.1 wt % titanium, equal to or less than about 0.5 wt % iron, equal to or less than about 0.5 wt % manganese, and a balance of aluminum. The aluminum alloy is subjected to a solution heat treatment. The aluminum alloy is quenched, and the aluminum alloy is age hardened at an age hardening temperature ranging from about 140° C. to 175° C. for a time period ranging from about 3 hours to about 35 hours.
    Type: Application
    Filed: November 8, 2016
    Publication date: May 10, 2018
    Inventors: Bin Hu, Pan Wang, Qi Lu
  • Patent number: 9896746
    Abstract: A method for preparing element diffusion-type composite substrate and it belongs to the field of high-temperature coated superconductor substrate preparation. The rolled composite nickel-tungsten alloy substrate is heated and thermally insulated, meanwhile, both ends of the rolled substrate are applied with a low voltage and high current density pulse current. High-performance nickel-tungsten alloy composite substrate is obtained with the method in the present invention and the sandwich-like composite substrate has low ferromagnetism and high strength due to higher solute diffusion from inner layer to outer layer, yet which does not affect the formation of sharp cubic texture on the surface of the composite substrate.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: February 20, 2018
    Assignee: BEIJING UNIVERSITY OF TECHNOLOGY
    Inventors: Hongli Suo, Yichen Meng, Lin Ma, Min Liu, Yi Wang, Mangmang Gao, Hui Tian, Yaru Liang, Pan Wang, Faxue Peng, Jing Liu, Tiantian Wang
  • Publication number: 20180026091
    Abstract: A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.
    Type: Application
    Filed: September 18, 2017
    Publication date: January 25, 2018
    Inventors: Hsiu-Jung Yen, Jen-Pan Wang, Yu-Hong Pan, Chih-Fu Chang
  • Publication number: 20180002348
    Abstract: The present invention provides a novel phenothiazine-pyridine compound that is an effective photosensitizer useful for photodynamic therapy. Also provided is a method for inhibiting cell proliferation or for treating a disease involving inappropriate cell proliferation.
    Type: Application
    Filed: May 8, 2017
    Publication date: January 4, 2018
    Inventors: Chuanshan Xu, Qicai Xiao, Wing Nang Leung, Pan Wang, Hungkay Lee
  • Patent number: 9768243
    Abstract: A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Jung Yen, Jen-Pan Wang, Yu-Hong Pan, Chih-Fu Chang