Patents by Inventor Panagiotis Manolios

Panagiotis Manolios has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10437713
    Abstract: A system for equivalence class analysis-based automated requirements-based test case generation includes a control processor, a data store containing textual design requirements, a textual converter unit structured to convert the textual design requirements to a machine-readable version of design requirements, a requirement partition unit configured to partition the machine-readable design requirements into one or more sets of related design requirements, an equivalence class partition unit configured to process the machine-readable design requirements and input/output variables into a set of equivalence classes, an equivalence class analyzer unit structured to analyze the set of equivalence classes to generate equivalence class tests and identify uncovered input space, and a boundary class analyzer unit structured to identify boundaries of the equivalence classes and generate boundary value tests and robustness tests.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: October 8, 2019
    Assignee: General Electric Company
    Inventors: Panagiotis Manolios, Meng Li, Italo Romani De Oliveira, Augusto Marasca De Conto, Han Yu, Daniel Russell, Sundeep Roy
  • Patent number: 10346140
    Abstract: A method for model-based design of safety-critical software is disclosed. The method includes receiving natural-language software requirements, developing a specification model by implementing either semantic modeling or graphical modeling, applying formal requirements analysis to the specification model, auto generating requirements based and robustness test cases from the specification model, developing a design model based on the specification model, applying test cases to the design model, auto-generating source code using the design model, verifying the source code using both test cases and static analysis technology, and compiling executable object code from the verified source code. If a result of the analysis of the software specification or design models is not satisfactory then adjusting the specification or design model to correct any inconsistency, and repeating applying the analysis and test cases.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: July 9, 2019
    Assignee: General Electric Company
    Inventors: Timothy Lee Johnson, Andrew Walter Crapo, Michael Richard Durling, Alexander Walsch, Kit Yan Siu, Luca Parolini, Panagiotis Manolios, Meng Li, Han Yu, Scott Alan Stacey, Gregory Reed Sykes
  • Publication number: 20180300226
    Abstract: A system for equivalence class analysis-based automated requirements-based test case generation includes a control processor, a data store containing textual design requirements, a textual converter unit structured to convert the textual design requirements to a machine-readable version of design requirements, a requirement partition unit configured to partition the machine-readable design requirements into one or more sets of related design requirements, an equivalence class partition unit configured to process the machine-readable design requirements and input/output variables into a set of equivalence classes, an equivalence class analyzer unit structured to analyze the set of equivalence classes to generate equivalence class tests and identify uncovered input space, and a boundary class analyzer unit structured to identify boundaries of the equivalence classes and generate boundary value tests and robustness tests.
    Type: Application
    Filed: June 21, 2018
    Publication date: October 18, 2018
    Inventors: Panagiotis MANOLIOS, Meng LI, Italo ROMANI DE OLIVEIRA, Augusto Marasca De CONTO, Han YU, Daniel RUSSELL, Sundeep ROY
  • Patent number: 10025696
    Abstract: A system for equivalence class analysis-based automated requirements-based test case generation includes a control processor, a data store containing textual design requirements, a textual converter unit structured to convert the textual design requirements to a machine-readable version of design requirements, a requirement partition unit configured to partition the machine-readable design requirements into one or more sets of related design requirements, an equivalence class partition unit configured to process the machine-readable design requirements and input/output variables into a set of equivalence classes, an equivalence class analyzer unit structured to analyze the set of equivalence classes to generate equivalence class tests and identify uncovered input space, and a boundary class analyzer unit structured to identify boundaries of the equivalence classes and generate boundary value tests and robustness tests.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: July 17, 2018
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Panagiotis Manolios, Meng Li, Italo Oliveira, Augusto Marasca De Conto
  • Patent number: 9983902
    Abstract: A system and method of multi-level scheduling analysis for a general processing module of a real-time operating system. The method includes identifying any processes within respective partitions of the general processing module, for each identified process, determining if the process is local-time centric or global-time centric. The method converts global-time centric process to a local-time centric process, applies a single-level scheduling analysis technique to the processes of respective partitions, and transforms local-time based response times to global-time based response times. The method performs scheduling and response time analyses on one or more of the identified processes of respective partitions. The method can be performed on a synchronous and/or asynchronous system, and on a hierarchical scheduling system that includes a top level scheduler having a static-cyclic schedule and/or a general static schedule. A system and non-transitory computer-readable medium are also disclosed.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: May 29, 2018
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Gregory Reed Sykes, Kevin Jones, Hongwei Liao, Panagiotis Manolios
  • Publication number: 20180039514
    Abstract: Methods, apparatus, systems and articles of manufacture to facilitate efficient scheduling of digital tasks in a system are disclosed. Periodic and aperiodic tasks may be identified, an initial minimum required duration may be determined based on the periodic and aperiodic tasks, a finish-to-activate duration of the aperiodic task may be determined, a final minimum required duration may be determined based on the initial minimum required duration and the finish-to-activate duration, a time budget may be adjusted to be the final minimum required duration, and the aperiodic task may be activated within the time budget based on the finish-to-activate duration.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventors: Hongwei LIAO, Panagiotis MANOLIOS, Terrell Michael BRACE, Gregory Reed SYKES, Kevin J. JONES, Kit Yan SIU
  • Patent number: 9747079
    Abstract: According to some embodiments, a system includes a communication device operative to communicate with a user to obtain the one or more requirements associated with a specification model for a semantic module; a semantic module to receive the one or more requirements, store the one or more requirements and transform the one or more requirements into a semantic model; a specification module to receive the semantic model, store the semantic model, translate the semantic model and generate a specification model; a memory for storing program instructions; at least one specification model platform processor, coupled to the memory, and in communication with the specification module and the semantic module and operative to execute program instructions to: transform the one or more requirements into a semantic model by executing the semantic module; translate the semantic model into a graphical model by executing the specification module; and modify the graphical model by executing the specification module to generate
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: August 29, 2017
    Assignee: General Electric Company
    Inventors: Kit Yan Siu, Andrew Walter Crapo, Michael Richard Durling, Luca Parolini, Panagiotis Manolios, Han Yu, Scott Stacey
  • Publication number: 20170228309
    Abstract: A system for equivalence class analysis-based automated requirements-based test case generation includes a control processor, a data store containing textual design requirements, a textual converter unit structured to convert the textual design requirements to a machine-readable version of design requirements, a requirement partition unit configured to partition the machine-readable design requirements into one or more sets of related design requirements, an equivalence class partition unit configured to process the machine-readable design requirements and input/output variables into a set of equivalence classes, an equivalence class analyzer unit structured to analyze the set of equivalence classes to generate equivalence class tests and identify uncovered input space, and a boundary class analyzer unit structured to identify boundaries of the equivalence classes and generate boundary value tests and robustness tests.
    Type: Application
    Filed: February 9, 2016
    Publication date: August 10, 2017
    Inventors: Panagiotis MANOLIOS, Meng LI, Italo OLIVEIRA, Augusto Marasca De CONTO
  • Patent number: 9639450
    Abstract: According to some embodiments, a system and method are provided for analyzing formal system requirements for software and hardware components in a software and hardware component specification model comprising receiving at least one requirement defined using a formal notation; determining if each of the requirements is self-conflicting via execution of a self-conflicting module; determining if two or more requirements conflict with each other via execution of a set-conflicting module after execution of the self-conflicting module; identifying each requirement involved in a conflict and how the one or more requirements conflicts via execution of an error localization module; receiving an updated requirement; repetitively analyzing each updated requirement with the self-conflicting module and the set-conflicting module; and generating an indication that requirements analysis is complete for the one or more requirements and the one or more requirements is validated for use in software design.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: May 2, 2017
    Assignee: General Electric Company
    Inventor: Panagiotis Manolios
  • Publication number: 20170039039
    Abstract: A method for model-based design of safety-critical software is disclosed. The method includes receiving natural-language software requirements, developing a specification model by implementing either semantic modeling or graphical modeling, applying formal requirements analysis to the specification model, auto generating requirements based and robustness test cases from the specification model, developing a design model based on the specification model, applying test cases to the design model, auto-generating source code using the design model, verifying the source code using both test cases and static analysis technology, and compiling executable object code from the verified source code. If a result of the analysis of the software specification or design models is not satisfactory then adjusting the specification or design model to correct any inconsistency, and repeating applying the analysis and test cases.
    Type: Application
    Filed: August 5, 2015
    Publication date: February 9, 2017
    Inventors: Timothy Lee Johnson, Andrew Walter Crapo, Michael Richard Durling, Alexander Walsch, Kit Yan Siu, Luca Parolini, Panagiotis Manolios, Meng Li, Han Yu, Scott Alan Stacey, Gregory Reed Sykes
  • Publication number: 20160371167
    Abstract: According to some embodiments, a system and method are provided comprising a communication device operative to communicate with a user to obtain one or more requirements, wherein each requirement is defined using a formal notation; a requirements analysis module to receive the one or more requirements, store the one or more requirements, and analyze each requirement individually and two or more requirements in conjunction to determine whether a conflict exists in the one or more requirements; an error localization module to identify each requirement involved in the conflict and indicates how the one or more requirement conflicts; a memory for storing program instructions; at least one requirements analysis processor, coupled to the memory, and in communication with requirements analysis module and the error localization module and operative to execute program instructions to: analyze each requirement individually to determine if the requirement is self-conflicting by executing a self-conflicting module of the
    Type: Application
    Filed: June 17, 2015
    Publication date: December 22, 2016
    Inventor: Panagiotis Manolios
  • Publication number: 20160335115
    Abstract: A system and method of multi-level scheduling analysis for a general processing module of a real-time operating system. The method includes identifying any processes within respective partitions of the general processing module, for each identified process, determining if the process is local-time centric or global-time centric. The method converts global-time centric process to a local-time centric process, applies a single-level scheduling analysis technique to the processes of respective partitions, and transforms local-time based response times to global-time based response times. The method performs scheduling and response time analyses on one or more of the identified processes of respective partitions. The method can be performed on a synchronous and/or asynchronous system, and on a hierarchical scheduling system that includes a top level scheduler having a static-cyclic schedule and/or a general static schedule. A system and non-transitory computer-readable medium are also disclosed.
    Type: Application
    Filed: May 14, 2015
    Publication date: November 17, 2016
    Inventors: Gregory Reed Sykes, Kevin Jones, Hongwei Liao, Panagiotis Manolios
  • Publication number: 20160170714
    Abstract: According to some embodiments, a system includes a communication device operative to communicate with a user to obtain the one or more requirements associated with a specification model for a semantic module; a semantic module to receive the one or more requirements, store the one or more requirements and transform the one or more requirements into a semantic model; a specification module to receive the semantic model, store the semantic model, translate the semantic model and generate a specification model; a memory for storing program instructions; at least one specification model platform processor, coupled to the memory, and in communication with the specification module and the semantic module and operative to execute program instructions to: transform the one or more requirements into a semantic model by executing the semantic module; translate the semantic model into a graphical model by executing the specification module; and modify the graphical model by executing the specification module to generate
    Type: Application
    Filed: December 15, 2014
    Publication date: June 16, 2016
    Inventors: Kit Yan Siu, Andrew Walter Crapo, Michael Richard Durling, Luca Parolini, Panagiotis Manolios, Han Yu, Scott Stacey
  • Patent number: 8438513
    Abstract: A new method is presented for eliminating existential quantifiers from a Boolean CNF (Conjunctive Normal Form) formula. This new method designs circuits by solving a quantifier elimination problem (QEP) by using derivation of dependency sequents (DDS). This new method begins with a first quantified conjunctive normal form formula, determines dependency sequents for the left branch and the right branch of a branching variable, resolves dependency sequents derived in both branches, and designs a circuit using a current formula having less variables than the first quantified conjunctive normal formula. Utility of this method includes verification, in particular, determining reachability of a state of a design.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: May 7, 2013
    Assignee: Northeastern University
    Inventors: Evgueni I. Goldberg, Panagiotis Manolios