Abstract: A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor.

Abstract: Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.

Abstract: A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor.

Abstract: A method of forming an inductor. The method includes: forming a dielectric layer on a substrate; forming a lower trench in the dielectric layer; forming a liner in the lower trench and on the dielectric layer; forming a Cu seed layer over the liner; forming a resist layer on the Cu seed layer; forming an upper trench in the resist layer; electroplating Cu to completely fill the lower trench and at least partially fill the upper trench; removing the resist layer; selectively forming a passivation layer on all exposed Cu surfaces; selectively removing the Cu seed layer from regions of the liner; and removing the thus exposed regions of the liner from the dielectric layer, wherein a top surface of the inductor extends above a top surface of the dielectric layer, the passivation layer remaining on regions of sidewalls of the inductor above the top surface of the dielectric layer.

Abstract: Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 ?m and via openings filled with electroplated copper than is substantially free of internal seams or voids.

Abstract: Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

Abstract: Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.

Abstract: An inductor and a method of forming and the inductor, the method including: (a) providing a semiconductor substrate; (b) forming a dielectric layer on a top surface of the substrate; (c) forming a lower trench in the dielectric layer; (d) forming a resist layer on a top surface of the dielectric layer; (e) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and (f) completely filling the lower trench at least partially filling the upper trench with a conductor in order to form the inductor. The inductor including a top surface, a bottom surface and sidewalls, a lower portion of said inductor extending a fixed distance into a dielectric layer formed on a semiconductor substrate and an upper portion extending above said dielectric layer; and means to electrically contact said inductor.

Abstract: Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

Abstract: A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.

Abstract: A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ? or as high as 1/10. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process.

Abstract: An interconnection structure comprising a substrate having a dielectric layer with a via opening therein; a barrier layer located in the via opening; an interlayer of palladium and/or platinum on the barrier layer; and a layer of copper or copper alloy on the interlayer is provided.

Abstract: Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 &mgr;m and via openings filled with electroplated copper than is substantially free of internal seams or voids.

Abstract: Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 &mgr;m and via openings filled with electroplated copper than is substantially free of internal seams or voids.

Abstract: An apparatus for plating and planarizing metal on a substrate includes a plurality of dispensing segments, each having at least one hole for dispensing electroplating solution onto the substrate. The dispensing segments form a circular counterelectrode and are movable with respect to each other during an electroplating process, so that the counterelectrode has a variable diameter. The electroplating solution is thus dispensed on an annular portion of the substrate having a diameter corresponding to the diameter of the counterelectrode; accordingly, the variable-diameter counterelectrode permits localized delivery of the plating solution to the substrate.

Abstract: An apparatus for plating and planarizing metal on a substrate includes a plurality of dispensing segments, each having at least one hole for dispensing electroplating solution onto the substrate. The dispensing segments form a circular counterelectrode and are movable with respect to each other during an electroplating process, so that the counterelectrode has a variable diameter. The electroplating solution is thus dispensed on an annular portion of the substrate having a diameter corresponding to the diameter of the counterelectrode; accordingly, the variable-diameter counterelectrode permits localized delivery of the plating solution to the substrate.

Abstract: A uniformly thick oxide film on a substrate is formed by using an anodization apparatus which deposits a blanket precursor film on a surface of a substrate; provides electrical contact to the precursor film; moves the precursor film into contact with an electrolyte solution such that substantially all electrically conductive surfaces, e.g., pin contacts, the substrate edge and a backside of the substrate are electrically isolated from the electrolyte; ensures that the surface of the precursor film on the substrate is in direct contact with the electrolyte solution; and which applies an anodizing current and/or voltage between the precursor film and a counter electrode so as to compensate for a voltage drop resulting from the presence of the electrolyte.

Abstract: An interconnection structure comprising a substrate having a dielectric layer with a via opening therein; a barrier layer located in the via opening; an interlayer of palladium and/or platinum on the barrier layer; and a layer of copper or copper alloy on the interlayer is provided.

Abstract: A method for controlling the composition of a chemical bath in which predictive dosing is used to account for changes in the composition of the bath in which the operating characteristics of the process are partitioned into a plurality of operating modes and the consumption or generation of materials related to the process are determined empirically and additions of material are made as appropriate.

Abstract: An interconnection structure is provided wherein comprises a substrate having a dielectric layer with a via opening therein; wherein the opening has a barrier layer; and electrodeposited copper.