Patents by Inventor Pankaj DESHMUKH
Pankaj DESHMUKH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240176751Abstract: This disclosure provides systems, methods, and devices for memory systems that support operating a least portions of a memory core at a frequency lower than a memory clock to reduce power consumption and cost. In a first aspect, a memory controller includes a first core for scheduling a first memory operation for a first portion of a clock cycle of the memory clock and includes a second core for scheduling a second memory operation for a second portion of the clock cycle of the memory clock. Other aspects and features are also claimed and described.Type: ApplicationFiled: November 29, 2022Publication date: May 30, 2024Inventors: Pankaj Deshmukh, Shyamkumar Thoziyoor, Vishakh Balakuntalam Visweswara, Jungwon Suh, Subbarao Palacharla
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Publication number: 20240111424Abstract: Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently. Embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.Type: ApplicationFiled: December 4, 2023Publication date: April 4, 2024Inventors: Shyamkumar THOZIYOOR, Pankaj DESHMUKH, Jungwon SUH, Subbarao PALACHARLA
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Publication number: 20240087639Abstract: Mitigating or managing an effect known as “rowhammer” upon a DRAM device may include a memory controller receiving an activation count threshold value from the DRAM device. The memory controller may detect row activation commands directed to the DRAM device and count the number of the row activation commands. The memory controller may send a mitigative refresh command to the DRAM device based on the result of comparing the counted number of row activation commands with the received activation count threshold value.Type: ApplicationFiled: September 8, 2022Publication date: March 14, 2024Inventors: Victor VAN DER VEEN, Pankaj DESHMUKH, Behnam DASHTIPOUR, David HARTLEY
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Publication number: 20240078202Abstract: Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank, generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel, sending, from the memory controller, the first signal to the first memory device, generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel, and sending, from the memory controller, the second signal to the second memory device.Type: ApplicationFiled: September 6, 2022Publication date: March 7, 2024Inventors: Jungwon SUH, Pankaj DESHMUKH, Shyamkumar THOZIYOOR, Subbarao PALACHARLA
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Publication number: 20240062800Abstract: An effect known as “rowhammer” may be mitigated in a DRAM organized in sub-banks of two or more rows. Row activation commands directed to a sub-bank may be detected. The number of row activation commands occurring within a refresh window may be counted and compared with a threshold. When it is detected that the number of row activation commands within the refresh window exceeds the threshold, an additional refresh command may be provided to the DRAM.Type: ApplicationFiled: August 17, 2022Publication date: February 22, 2024Inventors: Victor Van Der Veen, Pankaj Deshmukh, Behnam Dashtipour, David Hartley, Mosaddiq Saifuddin
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Patent number: 11907141Abstract: Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank, generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel, sending, from the memory controller, the first signal to the first memory device, generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel, and sending, from the memory controller, the second signal to the second memory device.Type: GrantFiled: September 6, 2022Date of Patent: February 20, 2024Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Pankaj Deshmukh, Shyamkumar Thoziyoor, Subbarao Palacharla
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Patent number: 11893240Abstract: Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently. Embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.Type: GrantFiled: October 28, 2021Date of Patent: February 6, 2024Assignee: QUALCOMM IncorporatedInventors: Shyamkumar Thoziyoor, Pankaj Deshmukh, Jungwon Suh, Subbarao Palacharla
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Patent number: 11881862Abstract: A system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.Type: GrantFiled: August 17, 2021Date of Patent: January 23, 2024Assignee: QUALCOMM INCORPORATEDInventors: Udayakiran Kumar Yallamaraju, Xia Li, Pankaj Deshmukh, Vajram Ghantasala, Bin Yang, Vishal Mishra, Bharatheesha Sudarshan Jagirdar, Arun Sundaresan Iyer, Amod Phadke, Vanamali Bhat
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Publication number: 20230305971Abstract: A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.Type: ApplicationFiled: February 9, 2022Publication date: September 28, 2023Inventors: Pankaj Deshmukh, Shyamkumar Thoziyoor, Vishakh Balakuntalam Visweswara, Jungwon Suh, Subbarao Palacharla
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Publication number: 20230136996Abstract: Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently. Embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.Type: ApplicationFiled: October 28, 2021Publication date: May 4, 2023Inventors: Shyamkumar THOZIYOOR, Pankaj DESHMUKH, Jungwon SUH, Subbarao PALACHARLA
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Publication number: 20230058318Abstract: A system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.Type: ApplicationFiled: August 17, 2021Publication date: February 23, 2023Inventors: Udayakiran Kumar YALLAMARAJU, Xia LI, Pankaj DESHMUKH, Vajram GHANTASALA, Bin YANG, Vishal MISHRA, Bharatheesha Sudarshan JAGIRDAR, Arun Sundaresan IYER, Amod PHADKE, Vanamali BHAT
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Patent number: 11360897Abstract: Dynamic random access memory (DRAM) data may be accessed by a memory controller using a broadcast mode or a non-broadcast mode. In the broadcast mode, a first portion of data that is the subject of an access request and a second portion of the data that is the subject of the access request may be accessed concurrently via first and second pseudo-channels, respectively. In the non-broadcast mode, data that is the subject of the access request may be accessed via a selected one of the first and second pseudo-channels.Type: GrantFiled: April 15, 2021Date of Patent: June 14, 2022Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Pankaj Deshmukh, Michael Hawjing Lo, Shyamkumar Thoziyoor
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Publication number: 20220129200Abstract: A DRAM memory controller is provided that identifies a marker command directed to a given row in a DRAM. If a threshold probability is satisfied in response to an identification of the marker command, the DRAM memory controller commands the DRAM to refresh a neighboring row in the DRAM. The neighboring row may be a neighboring of the given row or of a recently-closed row.Type: ApplicationFiled: August 17, 2021Publication date: April 28, 2022Inventors: Victor VAN DER VEEN, Mosaddiq SAIFUDDIN, Pankaj DESHMUKH, Behnam DASHTIPOUR, David HARTLEY