Patents by Inventor Pankaj Mehra
Pankaj Mehra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230273749Abstract: A storage device includes: a storage controller to receive data from a host device, and to store the data in storage memory; and a reconfigurable integrated circuit communicably connected to the storage controller, and to accelerate logic operations executed on the data stored in the storage memory, the reconfigurable integrated circuit including: a first logic block to execute a static logic operation from among the logic operations; a second logic block to execute one or more dynamic logic operations from among the logic operations; and a plurality of memory buffers configured to store inputs and outputs of the first and second logic blocks.Type: ApplicationFiled: May 8, 2023Publication date: August 31, 2023Inventor: Pankaj Mehra
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Patent number: 11687279Abstract: A storage device includes: a storage controller to receive data from a host device, and to store the data in storage memory; and a reconfigurable integrated circuit communicably connected to the storage controller, and to accelerate logic operations executed on the data stored in the storage memory, the reconfigurable integrated circuit including: a first logic block to execute a static logic operation from among the logic operations; a second logic block to execute one or more dynamic logic operations from among the logic operations; and a plurality of memory buffers configured to store inputs and outputs of the first and second logic blocks.Type: GrantFiled: March 20, 2020Date of Patent: June 27, 2023Assignee: Samsung Electronics Co., Ltd.Inventor: Pankaj Mehra
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Publication number: 20210232339Abstract: A storage device includes: a storage controller to receive data from a host device, and to store the data in storage memory; and a reconfigurable integrated circuit communicably connected to the storage controller, and to accelerate logic operations executed on the data stored in the storage memory, the reconfigurable integrated circuit including: a first logic block to execute a static logic operation from among the logic operations; a second logic block to execute one or more dynamic logic operations from among the logic operations; and a plurality of memory buffers configured to store inputs and outputs of the first and second logic blocks.Type: ApplicationFiled: March 20, 2020Publication date: July 29, 2021Inventor: Pankaj Mehra
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Publication number: 20200357435Abstract: Disclosed herein are magnetic storage media with embedded disconnected circuits, and magnetic storage systems comprising such media. A magnetic storage media comprises a recording layer comprising a storage location, and an embedded disconnected circuit (EDC) configured to assist in at least one of writing to or reading from the storage location in response to a wireless activation signal. A magnetic storage system comprises a signal generator configured to generate a wireless activation signal, a magnetic storage media with a plurality of storage locations, and a write transducer and/or a read receiver. The magnetic storage media has at least one EDC configured to assist in writing to and/or reading from at least one of the plurality of storage locations in response to the wireless activation signal.Type: ApplicationFiled: May 26, 2020Publication date: November 12, 2020Applicant: Western Digital Technologies, Inc.Inventors: Pankaj MEHRA, Bernd LAMBERTS, Sridhar CHATRADHI, Jordan A. KATINE
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Patent number: 10811047Abstract: Disclosed herein are magnetic storage media with embedded disconnected circuits, and magnetic storage systems comprising such media. A magnetic storage media comprises a recording layer comprising a storage location, and an embedded disconnected circuit (EDC) configured to assist in at least one of writing to or reading from the storage location in response to a wireless activation signal. A magnetic storage system comprises a signal generator configured to generate a wireless activation signal, a magnetic storage media with a plurality of storage locations, and a write transducer and/or a read receiver. The magnetic storage media has at least one EDC configured to assist in writing to and/or reading from at least one of the plurality of storage locations in response to the wireless activation signal.Type: GrantFiled: May 26, 2020Date of Patent: October 20, 2020Assignee: Western Digital Technologies, Inc.Inventors: Pankaj Mehra, Bernd Lamberts, Sridhar Chatradhi, Jordan A. Katine
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Patent number: 10777225Abstract: Disclosed herein are methods of using embedded disconnected circuits (EDC) in magnetic storage media to assist in reading data from and writing data to the magnetic storage media. A wireless activation signal is used to activate an EDC in a magnetic storage media. Once activated, the EDC may assist to record data in and/or read data from one or more memory locations of the magnetic storage media.Type: GrantFiled: June 26, 2018Date of Patent: September 15, 2020Assignee: Western Digital Technologies, Inc.Inventors: Pankaj Mehra, Bernd Lamberts, Sridhar Chatradhi, Jordan A. Katine
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Patent number: 10672425Abstract: Disclosed herein are magnetic storage media with embedded disconnected circuits, and magnetic storage systems comprising such media. A magnetic storage media comprises a recording layer comprising a storage location, and an embedded disconnected circuit (EDC) configured to assist in at least one of writing to or reading from the storage location in response to a wireless activation signal. A magnetic storage system comprises a signal generator configured to generate a wireless activation signal, a magnetic storage media with a plurality of storage locations, and a write transducer and/or a read receiver. The magnetic storage media has at least one EDC configured to assist in writing to and/or reading from at least one of the plurality of storage locations in response to the wireless activation signal.Type: GrantFiled: June 26, 2018Date of Patent: June 2, 2020Assignee: Western Digital Technologies, Inc.Inventors: Pankaj Mehra, Bernd Lamberts, Sridhar Chatradhi, Jordan A. Katine
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Patent number: 10565123Abstract: A host compiles code to perform a set of one or more database operations on target and embeds an indication of whether the target data is randomly accessed data or sequentially accessed data. The compiled code is transmitted to the compute engine inside a memory system that maintains a first portion of memory for storing sequentially accessed data and a second portion of memory for storing randomly accessed data. The memory system (e.g. SSD) maintains reduced size L2P tables in volatile working memory by maintaining coarse L2P tables in the working memory for use with sequentially accessed data and maintaining fine L2P tables in the working memory for use with randomly accessed data. The compute engine uses the compiled code to perform the set of one or more database operations on the target data using the working memory.Type: GrantFiled: October 5, 2017Date of Patent: February 18, 2020Assignee: Western Digital Technologies, Inc.Inventors: Seung-Hwan Song, Arup De, Pankaj Mehra, Brian W. O'Krafka
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Patent number: 10459644Abstract: A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die, a local memory connected to (or part of) the controller and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations. When the memory system receives instructions to use the compute engine to perform data manipulation operations, the local memory is reallocated such that an amount of space allocated in the local memory for logical to physical translation information is changed based on the one or more data manipulation instructions.Type: GrantFiled: October 6, 2017Date of Patent: October 29, 2019Assignee: Western Digital Techologies, Inc.Inventors: Pankaj Mehra, Vidyabhushan Mohan
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Patent number: 10387303Abstract: A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations.Type: GrantFiled: August 9, 2017Date of Patent: August 20, 2019Assignee: Western Digital Technologies, Inc.Inventors: Pankaj Mehra, Vidyabhushan Mohan, Seung-Hwan Song, Dejan Vucinic, Chao Sun, Minghai Qin, Arup De
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Publication number: 20180373453Abstract: Disclosed herein are methods of using embedded disconnected circuits (EDC) in magnetic storage media to assist in reading data from and writing data to the magnetic storage media. A wireless activation signal is used to activate an EDC in a magnetic storage media. Once activated, the EDC may assist to record data in and/or read data from one or more memory locations of the magnetic storage media.Type: ApplicationFiled: June 26, 2018Publication date: December 27, 2018Applicant: Western Digital Technologies, Inc.Inventors: Pankaj MEHRA, Bernd LAMBERTS, Sridhar CHATRADHI, Jordan A. KATINE
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Publication number: 20180373452Abstract: Disclosed herein are magnetic storage media with embedded disconnected circuits, and magnetic storage systems comprising such media. A magnetic storage media comprises a recording layer comprising a storage location, and an embedded disconnected circuit (EDC) configured to assist in at least one of writing to or reading from the storage location in response to a wireless activation signal. A magnetic storage system comprises a signal generator configured to generate a wireless activation signal, a magnetic storage media with a plurality of storage locations, and a write transducer and/or a read receiver. The magnetic storage media has at least one EDC configured to assist in writing to and/or reading from at least one of the plurality of storage locations in response to the wireless activation signal.Type: ApplicationFiled: June 26, 2018Publication date: December 27, 2018Applicant: Western Digital Technologies, Inc.Inventors: Pankaj MEHRA, Bernd LAMBERTS, Sridhar CHATRADHI, Jordan A. KATINE
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Publication number: 20180358989Abstract: A memory system (e.g., a solid state drive, or SSD) uses application-aware ECC schemes to make use of the specifics of a database schema and analytic queries. Only the fields relevant to the query are decoded, other fields are largely ignored. Integrated interleaved (II) codes and product codes approaches are described. Compared to traditional ECC schemes that decode the entire records before any fields to be used by the analytics are available, the new application-aware ECC schemes may achieve orders of magnitudes throughput improvement and/or substantially lower decoder complexity.Type: ApplicationFiled: September 6, 2017Publication date: December 13, 2018Applicant: Western Digital Technologies, Inc.Inventors: Pankaj Mehra, Xinmiao Zhang
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Publication number: 20180293174Abstract: A host compiles code to perform a set of one or more database operations on target and embeds an indication of whether the target data is randomly accessed data or sequentially accessed data. The compiled code is transmitted to the compute engine inside a memory system that maintains a first portion of memory for storing sequentially accessed data and a second portion of memory for storing randomly accessed data. The memory system (e.g. SSD) maintains reduced size L2P tables in volatile working memory by maintaining coarse L2P tables in the working memory for use with sequentially accessed data and maintaining fine L2P tables in the working memory for use with randomly accessed data. The compute engine uses the compiled code to perform the set of one or more database operations on the target data using the working memory.Type: ApplicationFiled: October 5, 2017Publication date: October 11, 2018Applicant: Western Digital Technologies, Inc.Inventors: Seung-Hwan Song, Arup De, Pankaj Mehra, Brian W. O'Krafka
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Publication number: 20180121121Abstract: A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die, a local memory connected to (or part of) the controller and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations. When the memory system receives instructions to use the compute engine to perform data manipulation operations, the local memory is reallocated such that an amount of space allocated in the local memory for logical to physical translation information is changed based on the one or more data manipulation instructions.Type: ApplicationFiled: October 6, 2017Publication date: May 3, 2018Applicant: Western Digital Technologies, Inc.Inventors: Pankaj Mehra, Vidyabhushan Mohan
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Publication number: 20180052766Abstract: A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations.Type: ApplicationFiled: August 9, 2017Publication date: February 22, 2018Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Pankaj Mehra, Vidyabhushan Mohan, Seung-Hwan Song, Dejan Vucinic, Chao Sun, Minghai Qin, Arup De
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Patent number: 9798620Abstract: Techniques are disclosed relating to writing data across multiple storage blocks in a storage device. In one embodiment, physical erase blocks in a bank of a storage device are erasable. Ones of the physical erase blocks may be associated with different respective communication channels. In such an embodiment, a data stripe may be written across a set of physical erase blocks such that the set of physical erase blocks includes physical erase blocks of different banks and includes physical erase blocks associated with different communication channels. In some embodiments, a request to read a portion of the data stripe may be received. In response to the request, a determination may be made that one of the set of physical erase blocks is unavailable to service the request. The request may then be serviced by reassembling data of the unavailable physical erase block.Type: GrantFiled: August 1, 2014Date of Patent: October 24, 2017Assignee: SanDisk Technologies LLCInventors: Robert Wood, Jeremy Fillingim, Pankaj Mehra
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Patent number: 9405680Abstract: A system and method is described that accesses a network persistent memory unit (nPMU). One embodiment comprises a primary region corresponding to a predefined portion of a primary network persistent memory unit (nPMU) communicatively coupled to at least one client processor node via a communication system, wherein the primary region is assigned to a client process running on the client processor node and is configured to store information received from the client process; and a mirror region corresponding to a predefined portion of a mirror nPMU communicatively coupled to the client processor node via the communication system, wherein the mirror region is assigned to the client process and is configured to store the information received from the client process.Type: GrantFiled: December 10, 2010Date of Patent: August 2, 2016Assignee: Hewlett Packard Enterprise Development LPInventors: Samuel Fineberg, Pankaj Mehra, Roger Hansen
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Patent number: 9213609Abstract: A system is described that includes a network interface attached to a persistent memory unit. The persistent memory unit is configured to receive checkpoint data from a primary process, and to provide access to the checkpoint data for use in a backup process, which provides recovery capability in the event of a failure of the primary process. The network interface is configured to provide address translation information between virtual and physical addresses in the persistent memory unit. In other embodiments, the persistent memory unit is capable of storing multiple updates to the checkpoint state. The checkpoint state and the updates to the checkpoint state, if any, can be retrieved by the backup process periodically, or all at once upon failure of the primary process.Type: GrantFiled: December 16, 2003Date of Patent: December 15, 2015Assignee: Hewlett-Packard Development Company, L.P.Inventors: Roger Hansen, Pankaj Mehra, Sam Fineberg
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Publication number: 20150220385Abstract: Techniques are disclosed relating to writing data across multiple storage blocks in a storage device. In one embodiment, physical erase blocks in a bank of a storage device are erasable. Ones of the physical erase blocks may be associated with different respective communication channels. In such an embodiment, a data stripe may be written across a set of physical erase blocks such that the set of physical erase blocks includes physical erase blocks of different banks and includes physical erase blocks associated with different communication channels. In some embodiments, a request to read a portion of the data stripe may be received. In response to the request, a determination may be made that one of the set of physical erase blocks is unavailable to service the request. The request may then be serviced by reassembling data of the unavailable physical erase block.Type: ApplicationFiled: August 1, 2014Publication date: August 6, 2015Inventors: Bob Wood, Jeremy Fillingim, Pankaj Mehra