Patents by Inventor Pan-Suk Kwak
Pan-Suk Kwak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240155844Abstract: A semiconductor memory device includes a mold structure including gate electrodes stacked on a first substrate, a channel structure that penetrates a first region of the mold structure to cross the gate electrodes, a first through structure that penetrates a second region of the mold structure, and a second through structure that penetrates a third region of the mold structure. The mold structure further includes memory cell blocks extending in a first direction and spaced apart in a second direction, and a dummy block extending in the first direction and disposed between the memory cell blocks. Each of the memory cell blocks and the dummy block includes a cell region and an extension region arranged in the first direction. The first region is the cell region of one of the memory cell blocks, the second region is the extension region of the one of the memory cell blocks, and the third region is the extension region of the dummy block.Type: ApplicationFiled: January 17, 2024Publication date: May 9, 2024Inventors: Myung Hun Lee, Dong Ha Shin, Pan Suk Kwak, Dae Seok Byeon
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Patent number: 11950425Abstract: A mold structure includes gate electrodes stacked on a first substrate, a channel structure penetrating a first region of the mold structure to cross the gate electrodes, a first through structure penetrating a second region of the mold structure, and a second through structure penetrating a third region of the mold structure. The mold structure includes memory cell blocks extending in a first direction and spaced apart in a second direction, and a dummy block extending in the first direction and disposed between the memory cell blocks. Each of the memory cell and dummy blocks includes a cell region and an extension region arranged in the first direction. The first region is the cell region of one of the memory cell blocks, the second region is the extension region of the one of the memory cell blocks, and the third region is the extension region of the dummy block.Type: GrantFiled: May 6, 2021Date of Patent: April 2, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Myung Hun Lee, Dong Ha Shin, Pan Suk Kwak, Dae Seok Byeon
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Patent number: 11665907Abstract: A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.Type: GrantFiled: June 24, 2021Date of Patent: May 30, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-Hwa Yun, Pan-Suk Kwak, Chan-Ho Kim, Bong-Soon Lim
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Publication number: 20220190131Abstract: A nonvolatile memory device includes a peripheral logic structure including a peripheral circuit on a substrate, a horizontal semiconductor layer extending along an upper surface of the peripheral logic structure, stacked structures arranged in a first direction on the horizontal semiconductor layer and including interlayer insulating films and conductive films alternately stacked in a direction perpendicular to the substrate, a first opening disposed between the stacked structures and included in the horizontal semiconductor layer to expose a part of the peripheral logic structure and a second opening arranged in a second direction, which differs from the first direction, from the first opening, included in the horizontal semiconductor layer, and disposed adjacent to the first opening. The peripheral logic structure includes a control transistor overlapping the second opening in a plan view and controlling operation of the plurality of stacked structures.Type: ApplicationFiled: August 23, 2021Publication date: June 16, 2022Inventors: Kyung Min KO, Myung Hun LEE, Pan Suk KWAK, Dae Seok BYEON
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Publication number: 20220157845Abstract: A non-volatile memory chip comprises a cell region that includes a first surface, a second surface opposite to the first surface, a first cell structure, and a second cell structure spaced apart from the first cell structure; a peripheral circuit region on the first surface of the cell region, and that includes a first peripheral circuit connected to the first cell structure, a second peripheral circuit connected to the second cell structure, and a connection circuit between the first and second peripheral circuits; a through via between the first and second cell structures and that extends from the second surface of the cell region to the connection circuit of the peripheral circuit region; a redistribution layer that covers the through via on the second surface of the cell region, is connected to the through via, and extends along the second surface; and a chip pad connected to the redistribution layer.Type: ApplicationFiled: July 26, 2021Publication date: May 19, 2022Inventors: MIN JAE LEE, Jin Do Byun, Young-Hoon Son, Young Don Choi, Pan Suk Kwak, Myung Hun Lee, Jung Hwan Choi
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Publication number: 20220115394Abstract: A semiconductor memory device includes a mold structure including gate electrodes stacked on a first substrate, a channel structure that penetrates a first region of the mold structure to cross the gate electrodes, a first through structure that penetrates a second region of the mold structure, and a second through structure that penetrates a third region of the mold structure. The mold structure further includes memory cell blocks extending in a first direction and spaced apart in a second direction, and a dummy block extending in the first direction and disposed between the memory cell blocks. Each of the memory cell blocks and the dummy block includes a cell region and an extension region arranged in the first direction. The first region is the cell region of one of the memory cell blocks, the second region is the extension region of the one of the memory cell blocks, and the third region is the extension region of the dummy block.Type: ApplicationFiled: May 6, 2021Publication date: April 14, 2022Inventors: MYUNG HUN LEE, DONG HA SHIN, PAN SUK KWAK, DAE SEOK BYEON
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Patent number: 11296066Abstract: A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.Type: GrantFiled: July 24, 2020Date of Patent: April 5, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-Hwa Yun, Pan-Suk Kwak, Chan-Ho Kim, Bong-Soon Lim
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Publication number: 20210320116Abstract: A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.Type: ApplicationFiled: June 24, 2021Publication date: October 14, 2021Inventors: KYUNG-HWA YUN, PAN-SUK KWAK, CHAN-HO KIM, BONG-SOON LIM
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Patent number: 11075216Abstract: A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.Type: GrantFiled: June 21, 2019Date of Patent: July 27, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-Hwa Yun, Pan-Suk Kwak, Chan-Ho Kim, Bong-Soon Lim
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Patent number: 10964710Abstract: A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.Type: GrantFiled: January 30, 2020Date of Patent: March 30, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-kil Yun, Chan-ho Kim, Pan-suk Kwak, Hong-soo Jeon
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Publication number: 20200365574Abstract: A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.Type: ApplicationFiled: July 24, 2020Publication date: November 19, 2020Inventors: KYUNG-HWA YUN, PAN-SUK KWAK, CHAN-HO KIM, BONG-SOON LIM
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Publication number: 20200168620Abstract: A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.Type: ApplicationFiled: January 30, 2020Publication date: May 28, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Dong-kil Yun, Chan-ho Kim, Pan-suk Kwak, Hong-soo Jeon
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Publication number: 20200066744Abstract: A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.Type: ApplicationFiled: June 21, 2019Publication date: February 27, 2020Inventors: KYUNG-HWA YUN, PAN-SUK KWAK, CHAN-HO KIM, BONG-SOON LIM
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Patent number: 10559577Abstract: A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.Type: GrantFiled: March 7, 2018Date of Patent: February 11, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-kil Yun, Chan-ho Kim, Pan-suk Kwak, Hong-soo Jeon
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Patent number: 10446575Abstract: A three-dimensional (3D) nonvolatile memory includes a stacked structure that includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers. The stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, and a connection region between the first cell region and the second cell region. The connection region includes a first step portion that contacts the first cell region and has a stepped shape that descends in a direction approaching the second cell region, a second step portion that contacts the second cell region and has a stepped shape that descends in a direction approaching the first cell region, and a connection portion that connects the first cell region and the second cell region.Type: GrantFiled: June 21, 2018Date of Patent: October 15, 2019Assignee: SAMSUNG ELECTRONICS CO., LTDInventors: Chan-Ho Kim, Bong-Soon Lim, Pan-Suk Kwak, Hong-Soo Jeon
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Patent number: 10373972Abstract: A vertical memory device and a method of manufacturing the same, the device including a cell array including cell regions spaced apart from each other in a second direction, each cell region including a regularly arranged plurality of vertical channels; bit-lines extending in the second direction, the bit-lines being spaced apart from each other in a first direction crossing the second direction; and bit-line contacts respectively electrically connecting the vertical channels and the bit-lines, wherein each cell region includes a sub isolation region configured to electrically isolate the cell region in the second direction, the sub isolation region extending in the first direction, the vertical channels are classified into a plurality of types according to a distance from the sub isolation region in the second direction in each cell region, and the bit-line contacts are configured to electrically connect each bit-line to at least two vertical channels having different types.Type: GrantFiled: April 3, 2018Date of Patent: August 6, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: An-Soo Park, Sung-Hoon Kim, Pan-Suk Kwak
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Publication number: 20190139978Abstract: A three-dimensional (3D) nonvolatile memory includes a stacked structure that includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers. The stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, and a connection region between the first cell region and the second cell region. The connection region includes a first step portion that contacts the first cell region and has a stepped shape that descends in a direction approaching the second cell region, a second step portion that contacts the second cell region and has a stepped shape that descends in a direction approaching the first cell region, and a connection portion that connects the first cell region and the second cell region.Type: ApplicationFiled: June 21, 2018Publication date: May 9, 2019Inventors: CHAN-HO KIM, Bong-Soon Lim, Pan-Suk Kwak, Hong-Soo Jeon
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Publication number: 20190109149Abstract: A vertical memory device and a method of manufacturing the same, the device including a cell array including cell regions spaced apart from each other in a second direction, each cell region including a regularly arranged plurality of vertical channels; bit-lines extending in the second direction, the bit-lines being spaced apart from each other in a first direction crossing the second direction; and bit-line contacts respectively electrically connecting the vertical channels and the bit-lines, wherein each cell region includes a sub isolation region configured to electrically isolate the cell region in the second direction, the sub isolation region extending in the first direction, the vertical channels are classified into a plurality of types according to a distance from the sub isolation region in the second direction in each cell region, and the bit-line contacts are configured to electrically connect each bit-line to at least two vertical channels having different types.Type: ApplicationFiled: April 3, 2018Publication date: April 11, 2019Inventors: An-Soo PARK, Sung-Hoon KIM, Pan-Suk KWAK
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Publication number: 20190067308Abstract: A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.Type: ApplicationFiled: March 7, 2018Publication date: February 28, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Dong-kil YUN, Chan-ho KIM, Pan-suk KWAK, Hong-soo JEON
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Patent number: 10026747Abstract: A non-volatile memory device is provided as follows. A substrate has a peripheral circuit. A first semiconductor layer is disposed on the substrate. The first semiconductor layer includes a memory cell region. A first gate structure is disposed on the first semiconductor layer. The first gate structure includes a plurality of first gate electrodes stacked in a perpendicular direction to the first semiconductor layer and a plurality of vertical channel structures penetrating the plurality of first gate electrodes. The first gate structure is arranged in the memory cell region. A second gate structure is disposed on the substrate. The second gate structure includes a plurality of second gate electrodes stacked in the perpendicular direction to the first semiconductor layer. The second gate structure is arranged outside the memory cell region.Type: GrantFiled: August 17, 2016Date of Patent: July 17, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chul-Jin Hwang, Pan-Suk Kwak, Seok-Jun Ham