Patents by Inventor Paola Maria Granatieri

Paola Maria Granatieri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process for fabricating integrated multi-crystal silicon resistors in MOS technology, and integrated MOS device comprising multi-crystal silicon resistors
    Patent number: 6489664
    Abstract: A fabrication process and an integrated MOS device having multi-crystal silicon resisters are described. The process includes depositing a multi-crystal silicon layer on top of a single-crystal silicon body; forming silicon oxide regions on top of the multi-crystal silicon layer in zones where resistors are to be produced; depositing a metal silicide layer on top of and in contact with the multi-crystal silicon layer so as to form a double conductive layer; and shaping the conductive layer to form gate regions, of MOS transistors. During etching of the double conductive layer, the metal silicide layer on top of the silicon oxide regions is removed and the silicon oxide regions form masking regions for the multi-crystal silicon underneath, so as to form resistive regions having a greater resistivity than the gate regions.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: December 3, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventors: Danilo Re, Massimo Monselice, Paola Maria Granatieri
  • Process for fabricating integrated multi-crystal silicon resistors in MOS technology, and integrated MOS device comprising multi-crystal silicon resistors
    Publication number: 20010023966
    Abstract: A fabrication process and an integrated MOS device having multi-crystal silicon resisters are described. The process includes depositing a multi-crystal silicon layer on top of a single-crystal silicon body; forming silicon oxide regions on top of the multi-crystal silicon layer in zones where resistors are to be produced; depositing a metal silicide layer on top of and in contact with the multi-crystal silicon layer so as to form a double conductive layer; and shaping the conductive layer to form gate regions, of MOS transistors. During etching of the double conductive layer, the metal silicide layer on top of the silicon oxide regions is removed and the silicon oxide regions form masking regions for the multi-crystal silicon underneath, so as to form resistive regions having a greater resistivity than the gate regions.
    Type: Application
    Filed: May 24, 2001
    Publication date: September 27, 2001
    Inventors: Danilo Re, Massimo Monselice, Paola Maria Granatieri
  • Process for fabricating integrated multi-crystal silicon resistors in MOS technology, and integrated MOS device comprising multi-crystal silicon resistors
    Patent number: 6261916
    Abstract: A fabrication process and an integrated MOS device having multi-crystal silicon resisters are described. The process includes depositing a multi-crystal silicon layer on top of a single-crystal silicon body; forming silicon oxide regions on top of the multi-crystal silicon layer in zones where resistors are to be produced; depositing a metal silicide layer on top of and in contact with the multi-crystal silicon layer so as to form a double conductive layer; and shaping the conductive layer to form gate regions, of MOS transistors. During etching of the double conductive layer, the metal silicide layer on top of the silicon oxide regions is removed and the silicon oxide regions form masking regions for the multi-crystal silicon underneath, so as to form resistive regions having a greater resistivity than the gate regions.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: July 17, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Danilo Re, Massimo Monselice, Paola Maria Granatieri