Patents by Inventor Paolo Ienne
Paolo Ienne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9231594Abstract: New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels of cells with each cell consisting of a logic gate or the functional equivalent of a logic gate, one or more selectable inverters, and wherein the inputs of the logic block consist of the inputs to the logic gate or functional equivalent of the logic gate and inputs to the selectable inverters. The new logic blocks can map circuits more efficiently than LUTs, because they include multi-output blocks and can cover more logic depth due to the higher input and output bandwidth.Type: GrantFiled: August 13, 2014Date of Patent: January 5, 2016Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)Inventors: Hadi Parandeh Afshar, David Novo Bruna, Paolo Ienne Lopez, Grace Zgheib
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Publication number: 20140347096Abstract: New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels of cells with each cell consisting of a logic gate or the functional equivalent of a logic gate, one or more selectable inverters, and wherein the inputs of the logic block consist of the inputs to the logic gate or functional equivalent of the logic gate and inputs to the selectable inverters. The new logic blocks can map circuits more efficiently than LUTs, because they include multi-output blocks and can cover more logic depth due to the higher input and output bandwidth.Type: ApplicationFiled: August 13, 2014Publication date: November 27, 2014Inventors: Hadi Parandeh Afshar, David Novo Bruna, Paolo Ienne Lopez, Grace Zgheib
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Patent number: 8836368Abstract: New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is an AND-Inverter Cone (AIC), which is a binary tree including one or more AND gates with a programmable conditional inversion and a number of intermediary outputs. Compared to LUTs, AICs are richer in terms of input and output bandwidth, because the area of the AICs grows only linearly with the number of inputs. Also, the delay grows only logarithmically with the input count. The new logic blocks can map circuits more efficiently than LUTs, because the AICs are multi-output blocks and can cover more logic depth due to the higher input bandwidth.Type: GrantFiled: December 21, 2011Date of Patent: September 16, 2014Assignee: Ecole Polytechnique Federale de Lausanne (EPFL)Inventors: Hadi Parandeh Afshar, David Novo Bruña, Paolo Ienne Lopez
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Patent number: 8667046Abstract: A Generalized Programmable Counter Array (GPCA) is a reconfigurable multi-operand adder, which can be reprogrammed to sum a plurality of operands of arbitrary size. The GPCA is configured to compress the input words down to two operands using parallel counters. Resulting operands are then summed using a standard Ripple Carry Adder to produce the final result. The GPCA consists of a linear arrangement of identical compressor slices (CSlice).Type: GrantFiled: February 20, 2009Date of Patent: March 4, 2014Assignee: Ecole Polytechnique Federale de Lausanne/Service des Relations IndustriellesInventors: Philip Brisk, Alessandro Cevrero, Frank K. Gurkaynak, Paolo Ienne Lopez, Hadi Parandeh-Afshar
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Publication number: 20130162292Abstract: New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is an AND-Inverter Cone (AIC), which is a binary tree including one or more AND gates with a programmable conditional inversion and a number of intermediary outputs. Compared to LUTs, AICs are richer in terms of input and output bandwidth, because the area of the AICs grows only linearly with the number of inputs. Also, the delay grows only logarithmically with the input count. The new logic blocks can map circuits more efficiently than LUTs, because the AICs are multi-output blocks and can cover more logic depth due to the higher input bandwidth.Type: ApplicationFiled: December 21, 2011Publication date: June 27, 2013Applicant: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)Inventors: Hadi Parandeh Afshar, David Novo Bruña, Paolo Ienne Lopez
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Patent number: 8185716Abstract: A memory system comprises a first memory having associated therewith a first local memory access controller configured to access the first local memory using physical memory addresses and a second memory having associated therewith a second local memory access controller configured to access the second local memory using physical memory addresses. A global controller coupled to the first and second local controllers is configured to communicate virtual memory addresses to the first and second local memory controllers.Type: GrantFiled: October 22, 2007Date of Patent: May 22, 2012Assignee: Qimonda AGInventors: Maurizio Skerlj, Paolo Ienne Lopez
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Patent number: 8185696Abstract: Reconfigurable Systems-an-Chip (RSoCs) on the market consist of full-fledged processors and large Field-Programmable Gate Arrays (FPGAs). The latter can be used to implement the system glue logic, various peripherals, and application-specific coprocessors. Using FPGAs for application-specific coprocessors has certain speedup potentials, but it is less present in practice because of the complexity of interfacing the software application with the coprocessor. In the present application, we present a virtualisation layer consisting of an operating system extension and a hardware component. It lowers the complexity of interfacing and increases portability potentials, while it also allows the coprocessor to access the user virtual memory through a virtual memory window. The burden of moving data between processor and coprocessor is shifted from the programmer to the operating system.Type: GrantFiled: April 19, 2005Date of Patent: May 22, 2012Assignee: Ecole Polytechnique Federale de Lausanne (EPFL)Inventors: Miljan Vuletic, Laura Pozzi, Paolo Ienne
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Patent number: 8166467Abstract: Instruction Set Extensions (ISEs) can be used effectively to accelerate the performance of embedded processors. The critical, and difficult task of ISE selection is often performed manually by designers. A few automatic methods for ISE generation have shown good capabilities, but are still limited in the handling of memory accesses, and so they fail to directly address the memory wall problem. We present here the first ISE identification technique that can automatically identify state-holding Application-specific Functional Units (AFUs) comprehensively, thus being able to eliminate a large portion of memory traffic from cache and main memory. Our cycle-accurate results obtained by the SimpleScalar simulator show that the identified AFUs with architecturally visible storage gain significantly more than previous techniques, and achieve an average speedup of 2.8× over pure software execution.Type: GrantFiled: January 11, 2007Date of Patent: April 24, 2012Assignee: Ecole Polytechnique Federale De LausanneInventors: Partha Biswas, Laura Pozzi, Nikil Dutt, Paolo Ienne
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Publication number: 20110055521Abstract: Customisable embedded processors that are available on the market make it possible for designers to speed up execution of applications by using Application-specific Functional Units (AFUs), implementing Instruction-Set Extensions (ISEs). Furthermore, techniques for automatic ISE identification have been improving; many algorithms have been proposed for choosing, given the application's source code, the best ISEs under various constraints. Read and write ports between the AFUs and the processor register file are an expensive asset, fixed in the micro-architecture—some processors indeed only allow two read ports and one write port—and yet, on the other hand, a large availability of inputs and outputs to and from the AFUs exposes high speedup. Here we present a solution to the limitation of actual register file ports by serialising register file access and therefore addressing multi-cycle read and write.Type: ApplicationFiled: September 24, 2007Publication date: March 3, 2011Applicant: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)Inventors: Laura Pozzi, Paolo Ienne Lopez
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Patent number: 7844785Abstract: Access to a memory is optimized by monitoring physical memory addresses and by detecting a memory access conflict based on the monitored physical memory addresses. The data stored at a physical address for which a conflict was detected is transferred to a new physical address.Type: GrantFiled: October 22, 2007Date of Patent: November 30, 2010Assignee: Qimonda AGInventors: Maurizio Skerlj, Paolo Ienne Lopez
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Patent number: 7685587Abstract: Commercial data processors are available that include a capability of extending their instruction set for a specified application, i.e. of introducing customized functional units in the interest of enhanced processing performance. For such processors there is a need for automatically forming the extensions from high-level application code. A technique is described for selecting maximal-speedup convex subgraphs of the application dataflow graph under micro-architectural constraints.Type: GrantFiled: November 19, 2003Date of Patent: March 23, 2010Assignee: Ecole Polytechnique Federal de LausanneInventors: Laura Pozzi, Kubilay Atasu, Paolo Ienne Lopez
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Publication number: 20100005272Abstract: Reconfigurable Systems-an-Chip (RSoCs) on the market consist of full-fledged processors and large Field-Programmable Gate Arrays (FPGAs). The latter can be used to implement the system glue logic, various peripherals, and application-specific coprocessors. Using FPGAs for application-specific coprocessors has certain speedup potentials, but it is less present in practice because of the complexity of interfacing the software application with the coprocessor. In the present application, we present a virtualisation layer consisting of an operating system extension and a hardware component. It lowers the complexity of interfacing and increases portability potentials, while it also allows the coprocessor to access the user virtual memory through a virtual memory window. The burden of moving data between processor and coprocessor is shifted from the programmer to the operating system.Type: ApplicationFiled: April 19, 2005Publication date: January 7, 2010Inventors: Miljan Vuletic, Laura Pozzi, Paolo Ienne
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Publication number: 20090216826Abstract: A Generalized Programmable Counter Array (GPCA) is a reconfigurable multi-operand adder, which can be reprogrammed to sum a plurality of operands of arbitrary size. The GPCA is configured to compress the input words down to two operands using parallel counters. Resulting operands are then summed using a standard Ripple Carry Adder to produce the final result. The GPCA consists of a linear arrangement of identical compressor slices (CSlice).Type: ApplicationFiled: February 20, 2009Publication date: August 27, 2009Applicant: Ecole Polytechnique Federale de Lausanne/ Service des Relations Industrielles(SRI)Inventors: Philip Brisk, Alessandro Cevrero, Frank K. Gurkaynak, Paolo Ienne Lopez, Hadi Parandeh-Afshar
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Publication number: 20090106507Abstract: A memory system comprises a first memory having associated therewith a first local memory access controller configured to access the first local memory using physical memory addresses and a second memory having associated therewith a second local memory access controller configured to access the second local memory using physical memory addresses. A global controller coupled to the first and second local controllers is configured to communicate virtual memory addresses to the first and second local memory controllers.Type: ApplicationFiled: October 22, 2007Publication date: April 23, 2009Inventors: Maurizio Skerlj, Paolo Ienne Lopez
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Publication number: 20070162900Abstract: Instruction Set Extensions (ISEs) can be used effectively to accelerate the performance of embedded processors. The critical, and difficult task of ISE selection is often performed manually by designers. A few automatic methods for ISE generation have shown good capabilities, but are still limited in the handling of memory accesses, and so they fail to directly address the memory wall problem. We present here the first ISE identification technique that can automatically identify state-holding Application-specific Functional Units (AFUs) comprehensively, thus being able to eliminate a large portion of memory traffic from cache and main memory. Our cycle-accurate results obtained by the SimpleScalar simulator show that the identified AFUs with architecturally visible storage gain significantly more than previous techniques, and achieve an average speedup of 2.8× over pure software execution.Type: ApplicationFiled: January 11, 2007Publication date: July 12, 2007Inventors: Partha Biswas, Laura Pozzi, Nikil Dutt, Paolo Ienne
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Patent number: 6536003Abstract: The testable read-only memory for data memory redundant logic has read-only memory units for storage of determined fault addresses of faulty data memory units. The serviceability of each read-only memory unit can be checked by application of input test data and by comparison of read output test data with expected nominal output test data.Type: GrantFiled: February 8, 2000Date of Patent: March 18, 2003Assignee: Infineon Technologies AGInventors: Laurent Gaziello, Klaus Oberländer, Steffen Paul, Volker Schöber, Sabeen Randhawa, Paolo Ienne, Yannick Martelloni, Rod Fleck