Patents by Inventor Paolo Lanza

Paolo Lanza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process for obtaining multi-layer metallization of the back of a semiconductor substrate
    Patent number: 5342793
    Abstract: The metallization of the back of the semiconductor substrate is obtained by depositing a series of metal layers, after ion implantation of dopant on the interface with the first layer. The step of ion implantation is followed by the deposition of one or more metal layers of the aforesaid series, and then by thermal annealing under vacuum or in an inert atmosphere, at a temperature considerably lower than 500.degree. C. and for a period considerably shorter than 60 minutes.
    Type: Grant
    Filed: July 9, 1993
    Date of Patent: August 30, 1994
    Assignee: SGS-Thomson Microelectronics, S.R.L.
    Inventors: Antonello Santangelo, Carmelo Margo, Paolo Lanza
  • Metal-semiconductor ohmic contact forming process
    Patent number: 5302549
    Abstract: A metal semiconductor ohmic contact farming process consists of enrichment of the surface of the semiconductor on which contact is to be formed, by ion implantation of a dopant, followed by deposition of a metal film on the implanted surface and then by thermal annealing at a temperature lower than 500.degree. C. and for a period shorter than 60 minutes.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: April 12, 1994
    Assignee: SGS-Thompson Microelectronics S.r.L.
    Inventors: Antonello Santangelo, Carmelo Magro, Guiseppe Ferla, Paolo Lanza
  • Process for the manufacture of power-MOS semiconductor devices
    Patent number: 5141883
    Abstract: A process for the manufacture of power-MOS semiconductor devices achieves high cell density by the use of self-aligning techniques and photographic exposure equipment of the stepper type. The process calls for definition and formation of the source by a complementary spacer technique and metallization of the source and gate contact areas by silicides after formation of spacers on the gate wall.
    Type: Grant
    Filed: December 24, 1990
    Date of Patent: August 25, 1992
    Assignee: SGS-Thomson Microelectronics S.r.L.
    Inventors: Giuseppe Ferla, Carmelo Magro, Paolo Lanza
  • Process for defining and forming an active region of very limited dimensions in a semiconductor layer
    Patent number: 5130272
    Abstract: Along the outline of a first doped region, a first mask is formed. The mask is made up of a dielectric opposed to the oxygen diffusion. Another mask is created within this first mask, using a process of selective thermal oxidation. The second mask is used to implant dopant in a second region which will only be defined along the outlines of the first region.
    Type: Grant
    Filed: July 9, 1991
    Date of Patent: July 14, 1992
    Assignee: SGS-Thomson Microelectronics S.r.L.
    Inventors: Giuseppe Ferla, Paolo Lanza, Carmelo Magro