Abstract: A method for secure communication between a local area network and a wide area network includes integrating a NAT functionality in a firewall associated with the local area network, wherein the NAT functionality is suitable to translate the source port of outgoing data packets with a NAT port value obtained by adding to a NAT offset value the value of the session ED used in a session database. When reply data packets coming from the wide area network are received by the firewall, the session ID is extracted from the NAT port value and is used for directly pointing to the session database, thus reducing the time required to recognize the session.

Abstract: A method for secure communication between a local area network and a wide area network includes integrating a NAT functionality in a firewall associated with the local area network, wherein the NAT functionality is suitable to translate the source port of outgoing data packets with a NAT port value obtained by adding to a NAT offset value the value of the session ED used in a session database. When reply data packets coming from the wide area network are received by the firewall, the session ID is extracted from the NAT port value and is used for directly pointing to the session database, thus reducing the time required to recognize the session.

Abstract: A device and a method for aligning in time two essentially isochronous digital signals are provided, in which a plurality (2.sup.n) of replicas (CK1-CK4) of the first signal (CKIN), separated by a given phase difference, are generated and a number of said replicas (CK3, CK4) is subjected to sampling (4, 5) in correspondence with the rising edges of the second signal (DATA). As the result of the sampling, a combination of logic signals (SL0, SL1) is obtained which is representative of the phase relation existing between each of said replicas (CK1-CK4) and the second signal (DATA). The output signal (CKOUT) of the device, aligned with the second signal, corresponds to the one, among the replicas (CK1-CK4) of the first signal, which best reproduces the desired alignment condition.

Abstract: A circuit source has bias and modulation current generators for both p-type and n-type optical sources, and a pair of sources of control voltages for the bias and modulation current generators, which obtain pairs of control voltages from an adjustable driving current. An external signal allows selecting, by means of a control logic and CMOS gates, the generators required by the source. The circuit is made by using three pads of an integrated circuit, one for each control voltage source and the third comprising the current generators, the CMOS gates and the control logic.

Abstract: The serializing-parallelizing circuit comprises, on a single integrated circuit chip (IC), a transmitter (TX) which performs the parallel-to-series conversion of the data stream, the insertion into the serial stream, with a pre-set periodicity, of a synchronism word, and the line coding of the serial stream, and a receiver (RX) in which clock signals synchronous with the data stream are extracted from a serial stream of coded data and in which the data are decoded and the decoded signals undergo series-to-parallel conversion. The transmitter (TX) and the receiver (RX) can be configured to operate with 4 or 8-bit parallelism.

Abstract: The circuit in CMOS technology allows high speed driving of optical sources, in particular laser diodes, operating efficiently at speeds that meet the requirements imposed by optical fiber communication systems and avoiding interference between driving currents and biasing current in the optical source. The circuit utilizes a bias current generator, a modulation current generator and a cascade of CMOS inverter stages that supplies a driving voltage to the modulation current generator and receives digital signals at its input. It is possible to independently adjust the bias current, so as to allow driving sources with different threshold currents, and to adjust the modulation current.