Patents by Inventor Para Kanagasabai Segaram

Para Kanagasabai Segaram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100165562
    Abstract: A sub system for a computing device comprising a plurality of chips mounted on a foldable substrate wherein the foldable substrate and the chips are layered by folding the substrate whereby the chips are disposed in at least one stacked configuration and wherein the sub system is adapted to be received on a host board. In addition, removable connections using resilient and nanostructure based members.
    Type: Application
    Filed: January 12, 2007
    Publication date: July 1, 2010
    Inventor: Para Kanagasabai Segaram
  • Patent number: 7240052
    Abstract: The generation a search query based on information stored on a storage medium is described. According to one embodiment of the invention, search criteria is entered to perform a search of a storage medium of a client computer. The search of the storage medium determines a web search criteria. The client computer provides search results based on the web search criteria.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: July 3, 2007
    Assignee: IAC Search & Media, Inc.
    Inventors: Jeffrey Alan Joseph Sidlosky, Creighton W. Chong, Inessa Obenhuber, legal representative, Para Kanagasabai Segaram, Thomas J. Obenhuber, deceased
  • Patent number: 6933610
    Abstract: In a semiconductor device having a semiconductor die without an ESD circuit and a separate ESD circuit and an external lead, the external lead is first bonded to the separate ESD circuit. Thereafter, the separate ESD circuit is bonded to the semiconductor die. As a result, in the process of bonding the semiconductor die, any ESD disturbance is absorbed by the ESD circuit. In addition, a semiconductor device such as a DDR DRAM memory device, has a chip carrier with a first surface having a plurality of leads and a second surface opposite to it with an aperture between them. A semiconductor die with a mounting surface and a bonding pad faces the second surface with the bonding pad in the aperture. An ESD circuit is mounted on the mounting surface in the aperture. A first electrical connector connects one of a plurality of leads to the ESD circuit and a second electrical connector connects the ESD circuit to the bonding pad.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: August 23, 2005
    Assignee: Silicon Pipe, Inc.
    Inventors: Para Kanagasabai Segaram, Joseph Fjelstad, Belgacem Haba
  • Publication number: 20030205802
    Abstract: In a semiconductor device having a semiconductor die without an ESD circuit and a separate ESD circuit and an external lead, the external lead is first bonded to the separate ESD circuit. Thereafter, the separate ESD circuit is bonded to the semiconductor die. As a result, in the process of bonding the semiconductor die, any ESD disturbance is absorbed by the ESD circuit. In addition, a semiconductor device such as a DDR DRAM memory device, has a chip carrier with a first surface having a plurality of leads and a second surface opposite to it with an aperture between them. A semiconductor die with a mounting surface and a bonding pad faces the second surface with the bonding pad in the aperture. An ESD circuit is mounted on the mounting surface in the aperture. A first electrical connector connects one of a plurality of leads to the ESD circuit and a second electrical connector connects the ESD circuit to the bonding pad.
    Type: Application
    Filed: February 19, 2003
    Publication date: November 6, 2003
    Inventors: Para Kanagasabai Segaram, Joseph Fjelstad, Belgacem Haba