Patents by Inventor Parag Dighe

Parag Dighe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Vectorized peak detection for signal processing
    Patent number: 10623222
    Abstract: Techniques related to a data processing engine for an integrated circuit (IC) are described. In an example, a method is provided for vectorized peak detection. The method includes dividing a set of data samples of a data signal, corresponding to a peak detection window (PDW), into a plurality of subsets of data samples each comprising a number of data samples. The method includes performing vector operations on each of the plurality of subsets of data samples. The method includes determining a running index of a sample with a maximum amplitude over the PDW based on the vector operations.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: April 14, 2020
    Assignee: XILINX, INC.
    Inventors: Kaushik Barman, Parag Dighe, Baris Ozgul, Sneha Bhalchandra Date
  • VECTORIZED PEAK DETECTION FOR SIGNAL PROCESSING
    Publication number: 20200076660
    Abstract: Techniques related to a data processing engine for an integrated circuit (IC) are described. In an example, a method is provided for vectorized peak detection. The method includes dividing a set of data samples of a data signal, corresponding to a peak detection window (PDW), into a plurality of subsets of data samples each comprising a number of data samples. The method includes performing vector operations on each of the plurality of subsets of data samples. The method includes determining a running index of a sample with a maximum amplitude over the PDW based on the vector operations.
    Type: Application
    Filed: August 30, 2018
    Publication date: March 5, 2020
    Applicant: Xilinx, Inc.
    Inventors: Kaushik Barman, Parag Dighe, Baris Ozgul, Sneha Bhalchandra Date
  • Multiplication of matrices using systolic arrays
    Patent number: 8924455
    Abstract: In one embodiment, a matrix multiplication circuit is provided. The circuit includes a plurality of systolic arrays, a pre-processing circuit, and a post-processing circuit. The pre-processing circuit is configured to receive first and second input matrices, and decompose the first input matrix into a plurality of sub-matrices. The pre-processing circuit inputs each of the plurality of sub-matrices to at least a respective one of the plurality of systolic arrays for multiplication with the second input matrix. The post-processing circuit is configured to combine output of the systolic arrays into a result matrix.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: December 30, 2014
    Assignee: Xilinx, Inc.
    Inventors: Kaushik Barman, Parag Dighe, Ragahavendar M. Rao