Patents by Inventor Parijat Biswas
Parijat Biswas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11853665Abstract: Hardware description language (HDL) code for an integrated circuit (IC) design may be parsed to obtain an IC design parse tree. A transformation pattern may include a first pattern and a second pattern. The transformation pattern may be parsed to obtain a transformation pattern parse tree. The IC design parse tree and the transformation pattern parse tree may be used to identify a portion of the HDL code that matches the first pattern. The identified portion of the HDL code may be transformed based on the second pattern to obtain a transformed portion of the HDL code. The portion of the HDL code may be replaced by the transformed portion of the HDL code.Type: GrantFiled: September 30, 2021Date of Patent: December 26, 2023Assignee: Synopsys, Inc.Inventors: Parijat Biswas, Minakshi Chakravorty, Sitikant Sahu
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Publication number: 20230409788Abstract: A system and method for using a distributed simulation system includes simulating a first portion of the circuit design within a first simulation environment by a first client device to generate first simulation data. Further, a second portion of the circuit design is simulated within a second simulation environment by a second client device to generate second simulation data. The first simulation data and the second simulation data are generated asynchronously with each other. Further, the first simulation data and the second simulation data are received at a primary client device synchronously with each other.Type: ApplicationFiled: June 21, 2022Publication date: December 21, 2023Inventors: Parijat BISWAS, Sitikant SAHU, Tilak Chand Vinay Kumar MEKA, Shivani JAIN
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Publication number: 20220108056Abstract: Hardware description language (HDL) code for an integrated circuit (IC) design may be parsed to obtain an IC design parse tree. A transformation pattern may include a first pattern and a second pattern. The transformation pattern may be parsed to obtain a transformation pattern parse tree. The IC design parse tree and the transformation pattern parse tree may be used to identify a portion of the HDL code that matches the first pattern. The identified portion of the HDL code may be transformed based on the second pattern to obtain a transformed portion of the HDL code. The portion of the HDL code may be replaced by the transformed portion of the HDL code.Type: ApplicationFiled: September 30, 2021Publication date: April 7, 2022Applicant: Synopsys, Inc.Inventors: Parijat Biswas, Minakshi Chakravorty, Sitikant Sahu
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Patent number: 11275877Abstract: Hardware simulation systems and methods for reducing signal dumping time and size of by fast dynamical partial aliasing of signals having similar waveform are provided. One example system is configured to receive, in real-time, a first signal from a producer entity; determine a first signal signature associated with the first signal; determine, in real-time, a second signal signature associated with the second signal; upon determining that the first signal signature matches the second signal signature, designate the first signal as a master signal and designate the second signal as a slave signal; and stop dumping the second signal to a storage space.Type: GrantFiled: September 27, 2019Date of Patent: March 15, 2022Assignee: Synopsys, Inc.Inventors: Parijat Biswas, Sitikant Sahu, Rahul Garg
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Patent number: 10831961Abstract: A data analysis engine is implemented in a testbench to improve coverage convergence during simulation of a device-under-validation (DUV). During a first simulation phase initial stimulus data is generated according to initial random variables based on user-provided constraint parameters. The data analysis engine then uses a time-based technique to match coverage variables sampled from simulation response data with corresponding initial random variables, determines a functional dependency (relationship) between the sampled coverage variables and corresponding initial random variables, then automatically generates revised constraint parameters based on the functional dependency. The revised constraint parameters are then used during a second simulation phase to generate focused random variables used to stimulate the DUV to reach additional coverage variables. In one embodiment, the functional dependency is determined by cross-correlating sampled coverage variables and corresponding initial random variables.Type: GrantFiled: July 12, 2019Date of Patent: November 10, 2020Assignee: Synopsys, Inc.Inventors: Esha Dutta, Danish Jawed, Bhaskar Pal, Parijat Biswas, Pravash Chandra Dash, Rajarshi Mukherjee, Sharad Gaur
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Publication number: 20200104443Abstract: Hardware simulation systems and methods for reducing signal dumping time and size of by fast dynamical partial aliasing of signals having similar waveform are provided. One example system is configured to receive, in real-time, a first signal from a producer entity; determine a first signal signature associated with the first signal; determine, in real-time, a second signal signature associated with the second signal; upon determining that the first signal signature matches the second signal signature, designate the first signal as a master signal and designate the second signal as a slave signal; and stop dumping the second signal to a storage space.Type: ApplicationFiled: September 27, 2019Publication date: April 2, 2020Inventors: Parijat Biswas, Sitikant Sahu, Rahul Garg
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Patent number: 10606977Abstract: The present invention provides a graphical view of this connected network that allows the user to navigate throughout a network. The graph view consists of a series of nodes that correspond to a set of test, testbench, design or coverage items in the simulation. Various nodes in the network are colored or shaped differently to represent either test, class, stimulus, testbench, design or coverage points. The graph may be drawn so that all items that occur at the same time are lined up in the same horizontal or vertical region, to give the user an intuitive view of time going left to right or top to bottom.Type: GrantFiled: July 14, 2017Date of Patent: March 31, 2020Assignee: SYNOPSYS, INC.Inventors: Alexander John Wakefield, Parijat Biswas, Pravash Chandra Dash, Sitikant Sahu, Sharad Nijhawan, Ractim Chakraborty, Manoharan Vellingiri
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Publication number: 20200019664Abstract: A data analysis engine is implemented in a testbench to improve coverage convergence during simulation of a device-under-validation (DUV). During a first simulation phase initial stimulus data is generated according to initial random variables based on user-provided constraint parameters. The data analysis engine then uses a time-based technique to match coverage variables sampled from simulation response data with corresponding initial random variables, determines a functional dependency (relationship) between the sampled coverage variables and corresponding initial random variables, then automatically generates revised constraint parameters based on the functional dependency. The revised constraint parameters are then used during a second simulation phase to generate focused random variables used to stimulate the DUV to reach additional coverage variables. In one embodiment, the functional dependency is determined by cross-correlating sampled coverage variables and corresponding initial random variables.Type: ApplicationFiled: July 12, 2019Publication date: January 16, 2020Applicant: Synopsys, Inc.Inventors: Esha Dutta, Danish Jawed, Bhaskar Pal, Parijat Biswas, Pravash Chandra Dash, Rajarshi Mukherjee, Sharad Gaur
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Patent number: 10521528Abstract: A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. The method comprises determining a value of the at least one output signal depending on the at least one input signal and determining a transfer function for computing the value of the output signal directly after a timestamp depending on the input signal and/or on the value of the output signal directly before the timestamp. The method further comprises computing the value of the at least one output signal directly after the timestamp as a function value of the transfer function, if a reconstruction condition is fulfilled.Type: GrantFiled: May 16, 2017Date of Patent: December 31, 2019Assignee: Synopsys, Inc.Inventors: Parijat Biswas, Shyam Datta, Subhrajyoti Chakraborty, Minakshi Chakravorty
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Publication number: 20170316118Abstract: The present invention provides a graphical view of this connected network that allows the user to navigate throughout a network. The graph view consists of a series of nodes that correspond to a set of test, testbench, design or coverage items in the simulation. Various nodes in the network are colored or shaped differently to represent either test, class, stimulus, testbench, design or coverage points. The graph may be drawn so that all items that occur at the same time are lined up in the same horizontal or vertical region, to give the user an intuitive view of time going left to right or top to bottom.Type: ApplicationFiled: July 14, 2017Publication date: November 2, 2017Inventors: Alexander Wakefield, Parijat Biswas, Pravash Chandra Dash, Sitikant Sahu, Sharad Nijhawan, Ractim Chakraborty, Manoharan Vellingiri
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Publication number: 20170255726Abstract: A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. The method comprises determining a value of the at least one output signal depending on the at least one input signal and determining a transfer function for computing the value of the output signal directly after a timestamp depending on the input signal and/or on the value of the output signal directly before the timestamp. The method further comprises computing the value of the at least one output signal directly after the timestamp as a function value of the transfer function, if a reconstruction condition is fulfilled.Type: ApplicationFiled: May 16, 2017Publication date: September 7, 2017Inventors: Parijat Biswas, Shyam Datta, Subhrajyoti Chakraborty, Minakshi Chakravorty
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Patent number: 9727678Abstract: The present invention provides a graphical view of this connected network that allows the user to navigate throughout a network. The graph view consists of a series of nodes that correspond to a set of test, testbench, design or coverage items in the simulation. Various nodes in the network are colored or shaped differently to represent either test, class, stimulus, testbench, design or coverage points. The graph may be drawn so that all items that occur at the same time are lined up in the same horizontal or vertical region, to give the user an intuitive view of time going left to right or top to bottom.Type: GrantFiled: March 13, 2014Date of Patent: August 8, 2017Assignee: SYNOPSYS, INC.Inventors: Alexander Wakefield, Pravash Chandra Dash, Sitikant Sahu, Sharad Nijhawan, Ractim Chakraborty, Manoharan Vellingiri, Parijat Biswas
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Patent number: 9684746Abstract: A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. The method comprises simulating a value of the at least one output signal depending on the at least one input signal and determining a transfer function for computing the value of the output signal directly after the simulation timestamp depending on the input signal and/or on the value of the output signal directly before the simulation timestamp. The method further comprises computing the value of the at least one output signal directly after the simulation timestamp as a function value of the transfer function, if a reconstruction condition is fulfilled.Type: GrantFiled: October 13, 2015Date of Patent: June 20, 2017Assignee: Synopsys, Inc.Inventors: Parijat Biswas, Shyam Datta, Subhrajyoti Chakraborty, Minakshi Chakravorty
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Publication number: 20170103152Abstract: A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. The method comprises simulating a value of the at least one output signal depending on the at least one input signal and determining a transfer function for computing the value of the output signal directly after the simulation timestamp depending on the input signal and/or on the value of the output signal directly before the simulation timestamp. The method further comprises computing the value of the at least one output signal directly after the simulation timestamp as a function value of the transfer function, if a reconstruction condition is fulfilled.Type: ApplicationFiled: October 13, 2015Publication date: April 13, 2017Inventors: Parijat Biswas, Shyam Datta, Subhrajyoti Chakraborty, Minakshi Chakravorty
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Publication number: 20140282315Abstract: The present invention provides a graphical view of this connected network that allows the user to navigate throughout a network. The graph view consists of a series of nodes that correspond to a set of test, testbench, design or coverage items in the simulation. Various nodes in the network are colored or shaped differently to represent either test, class, stimulus, testbench, design or coverage points. The graph may be drawn so that all items that occur at the same time are lined up in the same horizontal or vertical region, to give the user an intuitive view of time going left to right or top to bottom.Type: ApplicationFiled: March 13, 2014Publication date: September 18, 2014Applicant: Synopsys, Inc.Inventors: Alexander Wakefield, Pravash Chandra Dash, Sitikant Sahu, Sharad Nijhawan, Ractim Chakraborty, Manoharan Vellingiri, Parijat Biswas
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Patent number: 8443316Abstract: In a method for increasing coverage convergence during verification of a design for an IC, symbolic elements can be generated for the variables and the variable expressions in the hardware code of the design and a test bench. Simulation semantics can be modified and local multi-path analysis can be provided to expand symbolic property collection and symbolic element propagation. Modifying simulation semantics can include transformation of conditional statements, flattening of conditions, avoidance of short circuiting logic, and/or symbolic triggering of events. Symbolic elements are propagated through the design and the test bench during multiple simulation runs to collect symbolic properties. Coverage information from the multiple simulation runs is analyzed to identify coverage points to be targeted. For each identified coverage point, the constraints resulting from the collected symbolic properties are solved to generate directed stimuli for the design.Type: GrantFiled: November 9, 2011Date of Patent: May 14, 2013Assignee: Synopsys, Inc.Inventors: Parijat Biswas, Raghurama Krishna Srigiriraju, Alexandru Seibulescu, Gagan Vishal Jain
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Publication number: 20130117722Abstract: In a method for increasing coverage convergence during verification of a design for an IC, symbolic elements can be generated for the variables and the variable expressions in the hardware code of the design and a test bench. Simulation semantics can be modified and local multi-path analysis can be provided to expand symbolic property collection and symbolic element propagation. Modifying simulation semantics can include transformation of conditional statements, flattening of conditions, avoidance of short circuiting logic, and/or symbolic triggering of events. Symbolic elements are propagated through the design and the test bench during multiple simulation runs to collect symbolic properties. Coverage information from the multiple simulation runs is analyzed to identify coverage points to be targeted. For each identified coverage point, the constraints resulting from the collected symbolic properties are solved to generate directed stimuli for the design.Type: ApplicationFiled: November 9, 2011Publication date: May 9, 2013Applicant: Synopsys, Inc.Inventors: Parijat Biswas, Raghurama Krishna Srigiriraju, Alexandru Seibulescu, Gagan Vishal Jain
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Patent number: 8386974Abstract: In a method for increasing coverage convergence during verification of a design for an integrated circuit, multiple simulation runs can be performed. Symbolic variables and symbolic expressions can be generated for the variables and the variable expressions in the hardware code of the design and a test bench. Exemplary hardware code can include the hardware description language (HDL) code and/or the hardware verification language (HVL) code. Symbolic properties, which are derived from propagating the symbolic variables and symbolic expressions through the design and the test bench during the multiple simulation runs, can be collected. Coverage information from the multiple simulation runs can be analyzed to identify coverage points to be targeted. At this point, for each identified coverage point, the constraints resulting from the collected symbolic properties can be solved to generate directed stimuli for the design. These directed stimuli can increase the coverage convergence.Type: GrantFiled: April 14, 2011Date of Patent: February 26, 2013Assignee: Synopsys, Inc.Inventors: Parijat Biswas, Raghurama Krishna Srigiriraju, Alexandru Seibulescu, Jayant Nagda
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Publication number: 20120266118Abstract: In a method for increasing coverage convergence during verification of a design for an integrated circuit, multiple simulation runs can be performed. Symbolic variables and symbolic expressions can be generated for the variables and the variable expressions in the hardware code of the design and a test bench. Exemplary hardware code can include the hardware description language (HDL) code and/or the hardware verification language (HVL) code. Symbolic properties, which are derived from propagating the symbolic variables and symbolic expressions through the design and the test bench during the multiple simulation runs, can be collected. Coverage information from the multiple simulation runs can be analyzed to identify coverage points to be targeted. At this point, for each identified coverage point, the constraints resulting from the collected symbolic properties can be solved to generate directed stimuli for the design. These directed stimuli can increase the coverage convergence.Type: ApplicationFiled: April 14, 2011Publication date: October 18, 2012Applicant: Synopsys, Inc.Inventors: Parijat Biswas, Raghurama Krishna Srigiriraju, Alexandru Seibulescu, Jayant Nagda