Patents by Inventor Parimal GAIKWAD
Parimal GAIKWAD has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11640362Abstract: Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.Type: GrantFiled: April 12, 2021Date of Patent: May 2, 2023Assignee: Google LLCInventors: Shailendra Desai, Robert Totte, Juan Sierra, Parimal Gaikwad, Amit Jain, Mark Pearce
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Patent number: 11513892Abstract: A system, and corresponding method, is described for correcting an uncorrectable error in a coherent system. The uncorrectable error is detecting using an error detecting code, such as parity or SECDED. The cache controller or agent calculates a set of possible addresses. The directory is queried to determine which one of the set of possible addresses is the correct address. The agent and/or cache controller is updated with the correct address or way. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently correct errors and avoid a system restart when an uncorrectable error occurs.Type: GrantFiled: December 3, 2020Date of Patent: November 29, 2022Assignee: Arteris, Inc.Inventor: Parimal Gaikwad
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Patent number: 11416352Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.Type: GrantFiled: November 15, 2019Date of Patent: August 16, 2022Assignee: ARTERIS, INC.Inventors: Jean Philippe Loison, Benoit de Lescure, Alexis Boutiller, Rohit Bansal, Parimal Gaikwad, Mohammed Khaleeluddin
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Patent number: 11385957Abstract: A system, and corresponding method, is described for updating or calculating ECC where the transaction volume is significantly reduced from a read-modify-write to a write, which is more efficient and reduces demand on the data access bandwidth. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently communicate or exchange information.Type: GrantFiled: November 27, 2020Date of Patent: July 12, 2022Assignee: ARTERIS, INC.Inventor: Parimal Gaikwad
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Publication number: 20210294762Abstract: Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.Type: ApplicationFiled: April 12, 2021Publication date: September 23, 2021Applicant: Google LLCInventors: Shailendra DESAI, Robert TOTTE, Juan SIERRA, Parimal GAIKWAD, Amit JAIN, Mark PEARCE
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Patent number: 11003604Abstract: Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.Type: GrantFiled: March 29, 2019Date of Patent: May 11, 2021Assignee: PROVINO TECHNOLOGIES, INC.Inventors: Shailendra Desai, Robert Totte, Juan Sierra, Parimal Gaikwad, Amit Jain, Mark Pearce
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Publication number: 20210089396Abstract: A system, and corresponding method, is described for correcting an uncorrectable error in a coherent system. The uncorrectable error is detecting using an error detecting code, such as parity or SECDED. The cache controller or agent calculates a set of possible addresses. The directory is queried to determine which one of the set of possible addresses is the correct address. The agent and/or cache controller is updated with the correct address or way. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently correct errors and avoid a system restart when an uncorrectable error occurs.Type: ApplicationFiled: December 3, 2020Publication date: March 25, 2021Applicant: Arteris, Inc.Inventor: Parimal GAIKWAD
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Publication number: 20210081272Abstract: A system, and corresponding method, is described for updating or calculating ECC where the transaction volume is significantly reduced from a read-modify-write to a write, which is more efficient and reduces demand on the data access bandwidth. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently communicate or exchange information.Type: ApplicationFiled: November 27, 2020Publication date: March 18, 2021Applicant: Arteris, Inc.Inventor: Parimal GAIKWAD
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Patent number: 10877839Abstract: A system, and corresponding method, is described for correcting an uncorrectable error in a coherent system. The uncorrectable error is detecting using an error detecting code, such as parity or SECDED. The cache controller or agent calculates a set of possible addresses. The directory is queried to determine which one of the set of possible addresses is the correct address. The agent and/or cache controller is updated with the correct address or way. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently correct errors and avoid a system restart when an uncorrectable error occurs.Type: GrantFiled: December 28, 2017Date of Patent: December 29, 2020Assignee: ARTERIS, INC.Inventor: Parimal Gaikwad
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Patent number: 10866854Abstract: A system, and corresponding method, is described for updating or calculating ECC where the transaction volume is significantly reduced from a read-modify-write to a write, which is more efficient and reduces demand on the data access bandwidth. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently communicate or exchange information.Type: GrantFiled: September 22, 2017Date of Patent: December 15, 2020Assignee: ARTERIS, INC.Inventor: Parimal Gaikwad
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Publication number: 20200159631Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents.Type: ApplicationFiled: November 15, 2019Publication date: May 21, 2020Applicant: ARTERIS, INC.Inventors: Jean Philippe Loison, Benoit deLESCURE, Alexis BOUTILLER, Rohit BANSAL, Parimal GAIKWAD
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Patent number: 10592358Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.Type: GrantFiled: December 27, 2016Date of Patent: March 17, 2020Assignee: ARTERIS, INC.Inventors: Benoit deLescure, Jean Philippe Loison, Alexis Boutiller, Rohit Bansal, Parimal Gaikwad
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Patent number: 10585825Abstract: Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.Type: GrantFiled: March 29, 2019Date of Patent: March 10, 2020Assignee: PROVINO TECHNOLOGIES, INC.Inventors: Shailendra Desai, Robert Totte, Juan Sierra, Parimal Gaikwad, Amit Jain, Mark Pearce
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Patent number: 10452272Abstract: A system and method are disclosed with the ability to track usage of information, which patterns, and determine the most frequently used patterns to be stored and updated in a directory, thereby controlling and reducing the size allocated to storing information in the directory. The size is reduced by limiting address bits thereby allowing subsystems to avoid transmitting, storing, and operating upon excessive address information.Type: GrantFiled: December 27, 2016Date of Patent: October 22, 2019Assignee: ARTERIS, INC.Inventor: Parimal Gaikwad
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Patent number: 10452266Abstract: A system and method are disclosed with the ability to track usage of information and determine commonly used patterns to be stored and updated in a directory. The information includes counter values that represent the frequency of occurrence of a pattern that is committed to the directory. Thus, allows the system to control and reduce the size allocated to storing information in the directory because the size is reduced by limiting address bits. This, in turn, creates additional benefits in speed and power because it allows subsystems to avoid transmitting, storing, and operating upon excessive address information.Type: GrantFiled: December 27, 2016Date of Patent: October 22, 2019Assignee: ARTERIS, INC.Inventor: Parimal Gaikwad
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Publication number: 20190303217Abstract: Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.Type: ApplicationFiled: March 29, 2019Publication date: October 3, 2019Inventors: Shailendra Desai, Robert Totte, Juan Sierra, Parimal Gaikwad, Amit Jain, Mark Pearce
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Publication number: 20190303320Abstract: Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.Type: ApplicationFiled: March 29, 2019Publication date: October 3, 2019Inventors: Shailendra DESAI, Robert TOTTE, Juan SIERRA, Parimal GAIKWAD, Amit JAIN, Mark PEARCE
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Publication number: 20190095279Abstract: A system, and corresponding method, is described for correcting an uncorrectable error in a coherent system. The uncorrectable error is detecting using an error detecting code, such as parity or SECDED. The cache controller or agent calculates a set of possible addresses. The directory is queried to determine which one of the set of possible addresses is the correct address. The agent and/or cache controller is updated with the correct address or way. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently correct errors and avoid a system restart when an uncorrectable error occurs.Type: ApplicationFiled: December 28, 2017Publication date: March 28, 2019Applicant: Arteris, Inc.Inventor: Parimal GAIKWAD
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Patent number: 10146615Abstract: A system and method are disclosed that include recovery of the system directory when an uncorrectable error is detected. According to the various aspects and embodiments of the invention, the system and method disclosed can manage single bit error detection and two-bit error detection.Type: GrantFiled: April 24, 2017Date of Patent: December 4, 2018Assignee: ARTERIS, Inc.Inventor: Parimal Gaikwad
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Publication number: 20180307557Abstract: A system and method are disclosed that include recovery of the system directory when an uncorrectable error is detected. According to the various aspects and embodiments of the invention, the system and method disclosed can manage single bit error detection and two-bit error detection.Type: ApplicationFiled: April 24, 2017Publication date: October 25, 2018Applicant: Arteris, Inc.Inventor: Parimal GAIKWAD