Abstract: Techniques to partition a neural network model for serial execution on multiple processing integrated circuit devices are described. An initial partitioning of the model into multiple partitions each corresponding to a processing integrated circuit device is performed. For each partition, an execution latency is calculated by aggregating compute clock cycles to perform computations in the partition, and weight loading clock cycles determined based on a number of weights used in the partition. The amount of data being outputted from the partition is also determined. The partitions can be adjusted by moving computations from a source partition to a target partition to change execution latencies of the partitions and the amount of data being transferred between partitions.

Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.

Abstract: Implementing a circuit design may include detecting, using computer hardware, a net of the circuit design with a hold timing violation, generating, using the computer hardware, a list including each load of the net, and filtering, using the computer hardware, the list based on predetermined criteria by, at least in part, removing each load from the list determined to be non-critical with respect to hold timing. Using the computer hardware, the circuit design is modified by inserting a flip-flop in the net to drive each load remaining on the list, clocking the flip-flop with a clock signal of a start point or an end point of a path traversing the net, and triggering the flip-flop with an opposite clock edge compared to the start point or the end point.

Abstract: Disclosed approaches for fixing a hold time violation in a circuit design include determining a first hold budget that is an amount to fix a first hold time violation on a first path of the circuit design. For each connection of a first plurality of connections on the first path, a respective projected setup slack of the connection in allocating the first hold budget to fixing the first hold time violation on the connection is determined. For each connection of the first plurality of connections, a respective connection hold budget based on the first hold budget and the respective projected setup slack is determined. Each connection of the first plurality of connections is adjusted according to the respective connection hold budget.

Abstract: A method is provided for assigning signals to input pins of a component subject to asymmetric delays. A latency is determined for each signal-pin combination of the plurality of signals and plurality of input pins. The latency is determined as a function of an arrival time of the signal, a time to route the signal from to the input pin, and a time attributable to processing by the component. A latency threshold is selected. Signal to pin assignments using only signal-pin combinations having latencies less than or equal to the latency threshold are analyzed to determine if a one-to-one signal-to-pin assignment exists that includes all signals. The latency threshold is increased and the analysis is repeated until a valid one-to-one signal-to-pin assignment is found.

Abstract: A computer-implemented method of routing a circuit design for a target integrated circuit (IC) can include determining a characterization of routing congestion of the circuit design within the target IC and determining a first order cost component of using routing resources of the target IC according to the characterization. The method can include determining a higher order cost component of using routing resources of the target IC according to the characterization and assigning signals of the circuit design to routing resources according to costs calculated using the first order cost component and the higher order cost component. Signal assignments of the circuit design can be output.

Abstract: A method of assigning a plurality of input/output (I/O) objects of a circuit design to banks of a programmable integrated circuit (IC) using integer linear programming can include storing a plurality of constraints that depend upon a plurality of variables, wherein the plurality of constraints regulate assignment of each of the plurality of I/O objects to banks of the programmable IC (125-184), and storing a linear function that depends upon the plurality of constraints and a plurality of cost metrics, wherein each cost metric imposes a penalty when a selected I/O object of the circuit design is assigned to a bank of the programmable IC that is different from a bank to which the selected I/O object is assigned within a reference solution that is infeasible (190).

Abstract: A method of input/output (I/O) block placement assigned to an input/output bank includes formulating a placement algorithm using integer linear programming (ILP) and simultaneously placing single groups and Relatively Placed Module (RPM) groups of I/O blocks in the I/O bank. The method further includes determining a placeability matrix P and a binary assignment matrix X used for the ILP. The method can further eliminate all assignment matrix elements of X equal to 0 in the integer linear programming and re-index any remaining elements. The method can further place all I/O blocks according to a solution if solving of the standard ILP formulation results in a feasible solution. Optionally, the method generates a placement solution that is as close as possible to an external reference solution specified by designer. Optionally, the method analyzes which constraints were violated and generates useful error information.

Abstract: A method of placing a circuit design on a target device can include subdividing at least a portion of the circuit design into at least a first design-partition and a second design-partition separated by a design-cutline, and subdividing at least a portion of the target device into at least a first device-partition and a second device-partition separated by a device-cutline. The method can include determining a design-cutset corresponding to a design-cutline and calculating a measure of required wire-bandwidth for the device-cutline according to the design-cutset. The length of the design-cutline can be increased according to the measure of required wire-bandwidth, thereby altering the perimeter of the first device-partition and the perimeter of the second device-partition.

Abstract: A method of generating a low-skew network for a circuit design can include routing connections between a source and a plurality of loads of the network, determining a delay for at least one routed connection, and accepting the routed connections if the delay of each routed connection is within a skew tolerance range.

Abstract: A method of assigning input/output (I/O) objects of a circuit design to banks of a target device using integer linear programming can include assigning the I/O objects of the circuit design to I/O groups according to compatibility among the I/O objects, and establishing a plurality of relationships, comprising measures of bank capacity, regulating assignment of the I/O objects of I/O groups to banks of the target device. Each measure of bank capacity can indicate a maximum number of I/O objects from a selected I/O group that can be assigned to a selected bank of the target device. The method also can include determining whether a feasible solution exists for assignment of the I/O objects of the circuit design to banks of the target device by minimizing an object function while observing the plurality of relationships.

Abstract: A method of assigning I/O objects to banks of a target device can include concurrently assigning I/O objects, including select I/O objects and clock I/O objects, of the circuit design to I/O groups according to an I/O standard associated with each I/O object. Each I/O group can include only I/O objects of a same I/O standard. The method also can include establishing a plurality of linear constraints for regulating assignment of the I/O groups to banks of the target device. The linear constraints can include range constraints indicating I/O banks capable of hosting clock I/O objects. The method also can include defining mutual relationships among selected ones of the linear constraints. An indication as to whether a feasible solution exists for assignment of the I/O groups to banks of the target device can be provided by minimizing a linear objective function while observing the linear constraints and the mutual relationships.

Abstract: A method of global clock placement for a circuit design to be implemented on a programmable logic device (PLD) can include identifying clock properties for the circuit design and identifying physical clock region attributes for the PLD. The method further can include specifying an Integer Linear Programming formulation (ILP) of a clock placement problem for the circuit design from the clock properties and the physical clock region attributes. The ILP formulation can be solved to determine whether a feasible clock placement exists for the circuit design.