Patents by Inventor Partha Sriram
Partha Sriram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11899749Abstract: In various examples, training methods as described to generate a trained neural network that is robust to various environmental features. In an embodiment, training includes modifying images of a dataset and generating boundary boxes and/or other segmentation information for the modified images which is used to train a neural network.Type: GrantFiled: March 15, 2021Date of Patent: February 13, 2024Assignee: NVIDIA CORPORATIONInventors: Subhashree Radhakrishnan, Partha Sriram, Farzin Aghdasi, Seunghwan Cha, Zhiding Yu
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Publication number: 20220292306Abstract: In various examples, training methods as described to generate a trained neural network that is robust to various environmental features. In an embodiment, training includes modifying images of a dataset and generating boundary boxes and/or other segmentation information for the modified images which is used to train a neural network.Type: ApplicationFiled: March 15, 2021Publication date: September 15, 2022Inventors: Subhashree Radhakrishnan, Partha Sriram, Farzin Aghdasi, Seunghwan Cha, Zhiding Yu
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Publication number: 20210089921Abstract: Transfer learning can be used to enable a user to obtain a machine learning model that is fully trained for an intended inferencing task without having to train the model from scratch. A pre-trained model can be obtained that is relevant for that inferencing task. Additional training data, as may correspond to at least one additional class of data, can be used to further train this model. This model can then be pruned and retrained in order to obtain a smaller model that retains high accuracy for the intended inferencing task.Type: ApplicationFiled: September 23, 2020Publication date: March 25, 2021Inventors: Farzin Aghdasi, Varun Praveen, FNU Ratnesh Kumar, Partha Sriram
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Patent number: 8990280Abstract: In some embodiments, a data processing system including an operation unit including circuitry configurable to perform any selected one of a number of operations on data (e.g., audio data) and a configuration unit configured to assert configuration information to configure the operation unit to perform the selected operation. When the operation includes matrix multiplication of a data vector and a matrix whose coefficients exhibit symmetry, the configuration information preferably includes bits that determine signs of all but magnitudes of only a subset of the coefficients. When the operation includes successive addition and subtraction operations on operand pairs, the configuration information preferably includes bits that configure the operation unit to operate in an alternating addition/subtraction mode to perform successive addition and subtraction operations on each pair of data values of a sequence of data value pairs.Type: GrantFiled: November 14, 2006Date of Patent: March 24, 2015Assignee: Nvidia CorporationInventors: Partha Sriram, Robert Quan, Bhagawan Reddy Gnanapa, Ahmet Karakas
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Patent number: 8700387Abstract: Methods and systems for transcoding input audio data in a first encoding format to generate audio data in a second encoding format, and filterbanks for use in such systems. Some such systems include a combined synthesis and analysis filterbank (configured to generate transformed frequency-band coefficients indicative of at least one sample of the input audio data by transforming frequency-band coefficients in a manner equivalent to upsampling the frequency-band coefficients and filtering the resulting up-sampled values to generate the transformed frequency-band coefficients, where the frequency-band coefficients are partially decoded versions of input audio data that are indicative of the at least one sample) and a processing subsystem configured to generate transcoded audio data in the second encoding format in response to the transformed frequency-band coefficients.Type: GrantFiled: September 14, 2006Date of Patent: April 15, 2014Assignee: Nvidia CorporationInventors: Anil Ubale, Partha Sriram
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Patent number: 8666166Abstract: A method and system for performing a 2D transform is disclosed. The 2D transform may include a row transform and/or a column transform. When performing the row or column transform, it may be determined whether each of different subsets of the data values including a partition of a row or column includes at least one zero value, whether each of different subsets of a first subset of the partition includes at least one zero value, and whether each of different subsets of at least one other subset of the partition includes at least one zero value. When performing the row or column transform, at least one transformation operation on at least one zero value may be bypassed or performed in a reduced-power manner, where such transformation operation would otherwise be performed in a manner consuming full power if the zero value were a non-zero value.Type: GrantFiled: December 30, 2009Date of Patent: March 4, 2014Assignee: Nvidia CorporationInventors: Ravi Bulusu, Partha Sriram
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Patent number: 8660380Abstract: In some embodiments, a method for performing and a system configured to perform a 2D transform (for example, an inverse discrete cosine transform) on each block of a sequence of data blocks, where the 2D transform includes a row transform and a column transform. To perform the row or column transform on a row or column of data, these embodiments determine whether each of different subsets of the data values comprising a partition of the row (column) includes at least one zero value, whether each of different subsets of a first subset of the partition includes at least one zero value, and whether each of different subsets of at least one other subset of the partition includes at least one zero value.Type: GrantFiled: August 25, 2006Date of Patent: February 25, 2014Assignee: NVIDIA CorporationInventors: Ravi Bulusu, Partha Sriram
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Publication number: 20100104008Abstract: A method and system for performing a 2D transform is disclosed. The 2D transform may include a row transform and/or a column transform. When performing the row or column transform, it may be determined whether each of different subsets of the data values including a partition of a row or column includes at least one zero value, whether each of different subsets of a first subset of the partition includes at least one zero value, and whether each of different subsets of at least one other subset of the partition includes at least one zero value. When performing the row or column transform, at least one transformation operation on at least one zero value may be bypassed or performed in a reduced-power manner, where such transformation operation would otherwise be performed in a manner consuming full power if the zero value were a non-zero value.Type: ApplicationFiled: December 30, 2009Publication date: April 29, 2010Applicant: NVIDIA CORPORATIONInventors: Ravi Bulusu, Partha Sriram
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Patent number: 7605725Abstract: Systems and methods for optimizing system performance in variable length decoding systems are described. Embodiments are described in which decode tables are analyzed and elements of the tables sorted by probability of occurrence. Storage of elements can be determined by probability of occurrence and embodiments of the present invention can optimize system efficiency by storing most likely entries into fast-memory and least likely entries in slowest memory. In certain embodiments, a single large table is provided that cannot fit into decoder fast-memory. In some embodiments, individual elements can be optimized for storage in fast-memory by selecting more frequently occurring entries or groups of entries into decoder memory.Type: GrantFiled: January 29, 2008Date of Patent: October 20, 2009Assignee: NVIDIA CorporationInventors: Rohit Puri, Partha Sriram
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Publication number: 20080204287Abstract: Systems and methods for optimizing system performance in variable length decoding systems are described. Embodiments are described in which decode tables are analyzed and elements of the tables sorted by probability of occurrence. Storage of elements can be determined by probability of occurrence and embodiments of the present invention can optimize system efficiency by storing most likely entries into fast-memory and least likely entries in slowest memory. In certain embodiments, a single large table is provided that cannot fit into decoder fast-memory. In some embodiments, individual elements can be optimized for storage in fast-memory by selecting more frequently occurring entries or groups of entries into decoder memory.Type: ApplicationFiled: January 29, 2008Publication date: August 28, 2008Applicant: NVIDIA CORPORATIONInventors: Rohit Puri, Partha Sriram
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Patent number: 7372378Abstract: Methods and systems that leverage the advantages of Huffman coding to increase processing efficiency of a data-stream while simultaneously minimizing storage requirements are provided. Decoding efficiency and table storage requirements can be balanced to produce systems that can be adapted for use in high-end network infrastructure applications and for low-resourced portable consumer devices. The systems and methods are operative in decoding data streams using multi-symbol codes and sign information, including AAC and MP3 data streams. A hierarchical structure of tables is described as having primary tables, secondary tables, tertiary tables and so on. Optimization balances processing requirements, table storage requirements and the described systems and methods may be implemented on a variety of processing platforms.Type: GrantFiled: December 1, 2005Date of Patent: May 13, 2008Assignee: Nvidia CorporationInventor: Partha Sriram
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Publication number: 20080071528Abstract: Methods and systems for transcoding input audio data in a first encoding format to generate audio data in a second encoding format, and filterbanks for use in such systems. Some such systems include a combined synthesis and analysis filterbank (configured to generate transformed frequency-band coefficients indicative of at least one sample of the input audio data by transforming frequency-band coefficients in a manner equivalent to upsampling the frequency-band coefficients and filtering the resulting up-sampled values to generate the transformed frequency-band coefficients, where the frequency-band coefficients are partially decoded versions of input audio data that are indicative of the at least one sample) and a processing subsystem configured to generate transcoded audio data in the second encoding format in response to the transformed frequency-band coefficients.Type: ApplicationFiled: September 14, 2006Publication date: March 20, 2008Inventors: Anil Ubale, Partha Sriram
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Publication number: 20080050036Abstract: In some embodiments, a method for performing and a system configured to perform a 2D transform (for example, an inverse discrete cosine transform) on each block of a sequence of data blocks, where the 2D transform includes a row transform and a column transform. To perform the row or column transform on a row or column of data, these embodiments determine whether each of different subsets of the data values comprising a partition of the row (column) includes at least one zero value, whether each of different subsets of a first subset of the partition includes at least one zero value, and whether each of different subsets of at least one other subset of the partition includes at least one zero value.Type: ApplicationFiled: August 25, 2006Publication date: February 28, 2008Inventors: Ravi Bulusu, Partha Sriram
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Patent number: 7324026Abstract: Systems and methods for optimizing system performance in variable length decoding systems are described. Embodiments are described in which decode tables are analyzed and elements of the tables sorted by probability of occurrence. Storage of elements can be determined by probability of occurrence and embodiments of the present invention can optimize system efficiency by storing most likely entries into fast-memory and least likely entries in slowest memory. In certain embodiments, a single large table is provided that cannot fit into decoder fast-memory. In some embodiments, individual elements can be optimized for storage in fast-memory by selecting more frequently occurring entries or groups of entries into decoder memory.Type: GrantFiled: May 19, 2006Date of Patent: January 29, 2008Assignee: Nvidia CorporationInventors: Rohit Puri, Partha Sriram
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Publication number: 20070268166Abstract: Systems and methods for optimizing system performance in variable length decoding systems are described. Embodiments are described in which decode tables are analyzed and elements of the tables sorted by probability of occurrence. Storage of elements can be determined by probability of occurrence and embodiments of the present invention can optimize system efficiency by storing most likely entries into fast-memory and least likely entries in slowest memory. In certain embodiments, a single large table is provided that cannot fit into decoder fast-memory. In some embodiments, individual elements can be optimized for storage in fast-memory by selecting more frequently occurring entries or groups of entries into decoder memory.Type: ApplicationFiled: May 19, 2006Publication date: November 22, 2007Applicant: PortalPlayer, Inc.Inventors: Rohit Puri, Partha Sriram
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Publication number: 20070126608Abstract: Methods and systems that leverage the advantages of Huffman coding to increase processing efficiency of a data-stream while simultaneously minimizing storage requirements are provided. Decoding efficiency and table storage requirements can be balanced to produce systems that can be adapted for use in high-end network infrastructure applications and for low-resourced portable consumer devices. The systems and methods are operative in decoding data streams using multi-symbol codes and sign information, including AAC and MP3 data streams. A hierarchical structure of tables is described as having primary tables, secondary tables, tertiary tables and so on. Optimization balances processing requirements, table storage requirements and the described systems and methods may be implemented on a variety of processing platforms.Type: ApplicationFiled: December 1, 2005Publication date: June 7, 2007Applicant: PortalPlayer, Inc.Inventor: Partha Sriram
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Publication number: 20070078661Abstract: In some embodiments, a data processing system including an operation unit including circuitry configurable to perform any selected one of a number of operations on data (e.g., audio data) and a configuration unit configured to assert configuration information to configure the operation unit to perform the selected operation. When the operation includes matrix multiplication of a data vector and a matrix whose coefficients exhibit symmetry, the configuration information preferably includes bits that determine signs of all but magnitudes of only a subset of the coefficients. When the operation includes successive addition and subtraction operations on operand pairs, the configuration information preferably includes bits that configure the operation unit to operate in an alternating addition/subtraction mode to perform successive addition and subtraction operations on each pair of data values of a sequence of data value pairs.Type: ApplicationFiled: November 14, 2006Publication date: April 5, 2007Inventors: Partha Sriram, Robert Quan, Bhagawan Gnanapa, Ahmet Karakas