Abstract: According to one embodiment, a synchronous buck converter comprises a multi-mode control circuit for detecting a load condition of a variable load, an output stage driven by the multi-mode control circuit, wherein the variable load is coupled to the output stage, and a feedback circuit connected between the output stage and the multi-mode control circuit. The multi-mode control circuit is configured to adjust a current provided by the output stage to the variable load based on the load condition. In one embodiment, the multi-mode control circuit selectably uses one of at least a first control mode and a second control mode according to the load condition, wherein the first control mode is a pulse-width modulation (PWM) mode selected for switching efficiency when the load condition is heavy and the second control mode is an adaptive ON-time (AOT) mode selected for switching efficiency when the load condition is light.

Abstract: The rising edge of a pulse width modulated output signal occurs after an input ramp signal starts to rise. The ramp signal starts to rise after the rising edge of a periodic set signal and before the falling edge of a periodic set signal. A feedback control signal intersects a substantially linear region of the ramp signal to generate a reset signal using a PWM comparator. The periodic set signal and reset signal are input to a latching circuit to generate the pulse width modulated output signal. The minimum pulse width can approach zero while having adequate overdrive to the PWM comparator. Having the rising edge of the reset signal rise before the falling edge of the set signal can allow a zero percent duty cycle without the need for a ramp offset voltage.

Abstract: The rising edge of a pulse width modulated output signal occurs after an input ramp signal starts to rise. The ramp signal starts to rise after the rising edge of a periodic set signal and before the falling edge of a periodic set signal. A feedback control signal intersects a substantially linear region of the ramp signal to generate a reset signal using a PWM comparator. The periodic set signal and reset signal are input to a latching circuit to generate the pulse width modulated output signal. The minimum pulse width can approach zero while having adequate overdrive to the PWM comparator. Having the rising edge of the reset signal rise before the falling edge of the set signal can allow a zero percent duty cycle without the need for a ramp offset voltage.

Abstract: A pre-bias protection circuit for a converter circuit including a switching stage having high-and low-side switches connected in series at a switching node and an output stage connected to the switching node having a capacitor having a pre-existing pre-bias voltage at startup of the converter circuit, the pre-bias protection circuit controlling discharge of the pre-bias voltage when the low-side switch is turned ON during a start up of the converter circuit. The pre-bias protection circuit includes a first circuit for providing a first output; a second circuit providing a second output; and a comparator circuit for comparing the first output and the second output and producing a third output comprising a pulse width modulated signal for driving the low side switch such that the pulse width modulated signal starts with a small duty cycle and thereafter increases to a larger duty cycle, thereby to prevent the pre-bias voltage from discharging during startup.

Abstract: A pre-bias protection circuit for a converter circuit including a switching stage having high-and low-side switches connected in series at a switching node and an output stage connected to the switching node having a capacitor having a pre-existing pre-bias voltage at startup of the converter circuit, the pre-bias protection circuit controlling discharge of the pre-bias voltage when the low-side switch is turned ON during a start up of the converter circuit. The pre-bias protection circuit includes a first circuit for providing a first output; a second circuit providing a second output; and a comparator circuit for comparing the first output and the second output and producing a third output comprising a pulse width modulated signal for driving the low side switch such that the pulse width modulated signal starts with a small duty cycle and thereafter increases to a larger duty cycle, thereby to prevent the pre-bias voltage from discharging during startup.