Abstract: Method of wireless communication between a first device and a second device, in which, the first device and the second device comprising respectively a first thermoelectric generator and a second thermoelectric generator, the two thermoelectric generators being in thermal coupling, a first signal is generated within the first device, the first thermoelectric generator is electrically powered as a function of the first signal so as to create a first thermal gradient in the said first generator and a second thermal gradient in the second generator, and a second signal is generated within the second device on the basis of the electrical energy produced by the second thermoelectric generator in response to the said second thermal gradient.

Abstract: A method for producing an integrated circuit pointed element is disclosed. An element has a projection with a concave part directing its concavity towards the element. The element includes a first etchable material. A zone is formed around the concave part of the element. The zone includes a second material that is less rapidly etchable than the first material for a particular etchant. The first material and the second material are etched with the particular etchant to form an open crater in the concave part and thus to form a pointed region of the element.

Abstract: An EEPROM memory cell includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer. The insulation layer includes a first portion and a second portion having lower insulation properties than the first one. The second portion is located at least partially above a channel region of the transistor.

Abstract: An integrated circuit includes a substrate; an interconnect portion disposed over the substrate, the interconnect portion comprising multiple metallization levels separated by an insulating region; and an antifuse structure coated with a portion of the insulating region, the antifuse structure comprising a beam held at two different points by two arms, a body, and an antifuse insulating zone, the beam, the body and the arms being metal and located within a same metallization level, the body and the beam mutually making contact via the antifuse insulating zone, the antifuse insulating zone configured to undergo breakdown in the presence of a breakdown potential difference between the body and the beam.

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

Abstract: A fuse device is formed by a PN junction semiconducting region that is electrically insulated from other portions of an integrated circuit. The fuse device includes a first semiconducting zone having P type of conductivity and a second semiconducting zone having N type of conductivity in contact at a PN junction. First and second electrically conducting contact zones are provided on the first and second semiconducting zone, respectively, without making contact with the PN junction. One of the first and second semiconducting zones is configured with a non-homogeneous concentration of dopants, where a region with a lower value of concentration of dopant is located at the PN junction and a region with a higher value of concentration of dopant is locates at the corresponding electrically conducting contact zone.

Abstract: A device includes a thermally deformable assembly accommodated in a cavity of the interconnection part of an integrated circuit. The assembly can bend when there is a variation in temperature, so that its free end zone is displaced vertically. The assembly can be formed in the back end of line of the integrated circuit.

Abstract: A system, supplied by a power supply, is switched into standby mode by an electronic device that includes a charging input coupled to a charge voltage obtained from the voltage delivered by the power supply. A first input is coupled to the power supply and a power supply output is coupled to the system. A storage capacitive element is coupled to the charging input and configured to be charged by the charge voltage. A switching circuit, coupled between the first input and the power supply output, disconnects the power supply output from the first input when the voltage across the terminals of the storage capacitive element is higher than a threshold. A discharge circuit discharges the storage capacitive element so that the capacitor voltage becomes lower than the threshold. The switching circuit further re-connects the first input to the power supply output at the end of the discharge period.

Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.

Abstract: Method of wireless communication between a first device and a second device, in which, the first device and the second device comprising respectively a first thermoelectric generator and a second thermoelectric generator, the two thermoelectric generators being in thermal coupling, a first signal is generated within the first device, the first thermoelectric generator is electrically powered as a function of the first signal so as to create a first thermal gradient in the said first generator and a second thermal gradient in the second generator, and a second signal is generated within the second device on the basis of the electrical energy produced by the second thermoelectric generator in response to the said second thermal gradient.

Abstract: An integrated circuit includes a substrate; an interconnect portion disposed over the substrate, the interconnect portion comprising multiple metallization levels separated by an insulating region; and an antifuse structure coated with a portion of the insulating region, the antifuse structure comprising a beam held at two different points by two arms, a body, and an antifuse insulating zone, the beam, the body and the arms being metal and located within a same metallization level, the body and the beam mutually making contact via the antifuse insulating zone, the antifuse insulating zone configured to undergo breakdown in the presence of a breakdown potential difference between the body and the beam.

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

Abstract: A MOS transistor is produced on and in an active zone which includes a source region and a drain region. The active zone is surrounded by an insulating region. A conductive gate region of the transistor has two flanks which extend transversely to a source-drain direction, and the conductive gate region overlaps two opposite edges of the active zone act overlap zones. The conductive gate region includes, at a location of at least one overlap zone, at least one conductive tag which projects from at least one flank at a foot of the conductive gate region. The conductive tag covers a part of the active zone and a part of the insulating region.

Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.

Abstract: A device includes a thermally deformable assembly accommodated in a cavity of the interconnection part of an integrated circuit. The assembly can bend when there is a variation in temperature, so that its free end zone is displaced vertically. The assembly can be formed in the back end of line of the integrated circuit.

Abstract: A fuse device is formed by a PN junction semiconducting region that is electrically insulated from other portions of an integrated circuit. The fuse device includes a first semiconducting zone having P type of conductivity and a second semiconducting zone having N type of conductivity in contact at a PN junction. First and second electrically conducting contact zones are provided on the first and second semiconducting zone, respectively, without making contact with the PN junction. One of the first and second semiconducting zones is configured with a non-homogeneous concentration of dopants, where a region with a lower value of concentration of dopant is located at the PN junction and a region with a higher value of concentration of dopant is locates at the corresponding electrically conducting contact zone.

Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer. An electrical discontinuity between a first via of the via level and a first metal track of the lower metallization level is provided at the level of the insulating encapsulation layer. The electrical discontinuity is formed prior to formation of any via of the via level and prior to any metal track of the upper metallization level. The electrical discontinuity may comprise: a portion of an additional insulating layer extending over the insulating encapsulation layer; a portion of the insulating encapsulation layer; or an insulating oxide on a top surface of the first metal track.

Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer and an inter-metallization level insulating layer. An electrical discontinuity is provided between a via of the via level and a metal track of the lower metallization level. The electrical discontinuity is formed by an additional insulating layer having a material composition identical to that of the inter-metallization level insulating layer. The electrical discontinuity is situated between a bottom of the via and a top of the metal track, with the discontinuity being bordered by the insulating encapsulation layer.

Abstract: An integrated circuit, comprising an electrical-switching mechanical device in a housing having at least one first thermally deformable assembly including a beam held in at least two different locations by at least two arms secured to edges of the housing, the beam and the arms being metallic and situated within the same first metallization level and an electrically conductive body, wherein the said first thermally deformable assembly has at least one first configuration at a first temperature and a second configuration when at least one is at a second temperature different from the first temperature, wherein the beam is at a distance from the body in the first configuration and in contact with the said body and immobilized by the said body in the second configuration and establishing or prohibiting an electrical link passing through the body and through the beam.

Abstract: The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.