Patents by Inventor Pascal Gardes

Pascal Gardes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6830970
    Abstract: A method for manufacturing, in a monolithic circuit including a substrate, an inductance and a through via, including the step of forming, from a first surface of the substrate, at least one trench according to the contour of the inductance to be formed; forming by laser in the substrate a through hole at the location desired for the via; simultaneously insulating the surface of the trench and of the hole; and depositing a conductive material in the trench and at least on the hole walls.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: December 14, 2004
    Assignee: STMicroelectronics, S.A.
    Inventor: Pascal Gardes
  • Patent number: 6677657
    Abstract: A method for forming a component in a portion of a semiconductor substrate on insulator delimited by a lateral wall separated by an insulating layer from a peripheral region internal to the portion and heavily doped of a same first conductivity type as the substrate. A conductive plate is formed at the same time as the wall, on a layer of protection of the substrate surface, in electric contact with the peripheral region, the plate extending above said peripheral region towards the inside of the portion with respect to the wall, beyond the location above the limit between the peripheral region and the substrate.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: January 13, 2004
    Assignee: STMicroelectronics A.A.
    Inventor: Pascal Gardes
  • Publication number: 20030068884
    Abstract: A method for manufacturing, in a monolithic circuit comprising a substrate, an inductance and a through via, comprising the step of forming, from a first surface of the substrate, at least one trench according to the contour of the inductance to be formed; forming by laser in the substrate a through hole at the location desired for the via; simultaneously insulating the surface of the trench and of the hole; and depositing a conductive material in the trench and at least on the hole walls.
    Type: Application
    Filed: October 10, 2002
    Publication date: April 10, 2003
    Inventor: Pascal Gardes
  • Publication number: 20030066184
    Abstract: A method for manufacturing an inductance in a monolithic circuit including a substrate of planar upper surface, including the steps of forming in the substrate a cavity substantially following the contour of the inductance to be formed, the cross-section of the cavity being deep with respect to its width; and filling the cavity with a conductive material.
    Type: Application
    Filed: October 10, 2002
    Publication date: April 10, 2003
    Inventors: Pascal Gardes, Gerard Auriel
  • Publication number: 20030057485
    Abstract: A method for forming a component in a portion of a semiconductor substrate on insulator delimited by a lateral wall separated by an insulating layer from a peripheral region internal to the portion and heavily doped of a same first conductivity type as the substrate. A conductive plate is formed at the same time as the wall, on a layer of protection of the substrate surface, in electric contact with the peripheral region, the plate extending above said peripheral region towards the inside of the portion with respect to the wall, beyond the location above the limit between the peripheral region and the substrate.
    Type: Application
    Filed: September 26, 2002
    Publication date: March 27, 2003
    Inventor: Pascal Gardes
  • Publication number: 20030032294
    Abstract: A method for handling a thin silicon wafer including the steps of successively forming on a surface of the wafer a first protection layer, a first etch stop layer, and an external layer; forming on a surface of a support wafer a gluing layer of the same material as the external layer of the wafer, the surface of the support wafer including a plurality of pads, the respective upper portions of which are substantially planar and coplanar; fastening, by direct gluing, the external layer of the wafer and the gluing layer of the support wafer; processing the wafer to form circuits therein; depositing a second protection layer on the wafer surface which is not glued to the support wafer; and removing by an etch process the material forming the external layer of the wafer and the gluing layer of the support wafer.
    Type: Application
    Filed: August 13, 2002
    Publication date: February 13, 2003
    Inventor: Pascal Gardes