Patents by Inventor Pascal Gouraud
Pascal Gouraud has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240178055Abstract: The present description concerns a method of manufacturing an insulating trench in a substrate, for an electronic device, comprising the following successive steps: (a) filling a trench formed in the substrate with a first insulating material; (b) depositing a first etch stop layer on the first material; (c) depositing a second layer of a second insulating material on the first etch stop layer; (d) etching down to the etch stop layer; and (e) depositing a third layer made of a third tight material.Type: ApplicationFiled: November 14, 2023Publication date: May 30, 2024Applicant: STMicroelectronics (Crolles 2) SASInventors: Thierno Moussa BAH, Pascal GOURAUD, Patrick GROS D'AILLON, Emilie PREVOST
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Patent number: 11901216Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.Type: GrantFiled: October 7, 2021Date of Patent: February 13, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Pascal Gouraud, Delia Ristoiu
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Publication number: 20230178479Abstract: A method is presented for manufacturing an insulated conductive via. The via crosses a first stack of layers to reach a first layer. A first cavity is formed partially extending into the first stack of layers. A second stack of layers is formed over the first stack of layers and in the first cavity. The second stack of layers includes an etch stop layer and an insulating layer. A second cavity is then formed extending completely through first and second stacks of layers to reach the first layer. An insulating liner then covers the walls and bottom of the second cavity. The insulating liner is then anisotropically etched, and the second cavity is filled by a conductive material forming the core of the via.Type: ApplicationFiled: December 5, 2022Publication date: June 8, 2023Applicant: STMicroelectronics (Crolles 2) SASInventors: Marios BARLAS, Pascal GOURAUD
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Publication number: 20220384721Abstract: A memory cell is manufactured by: (a) forming a stack comprising a first layer made of a phase change material and a second layer made of a conductive material; (b) forming a mask on the stack covering only the memory cell location; and (c) etching portions of the stack not covered by the first mask. The formation of the mask covering only the memory cell location comprises defining a first mask extending in a row direction for each row of memory cell locations and then patterning the first mask in a column direction for each column of memory cell locations.Type: ApplicationFiled: May 23, 2022Publication date: December 1, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Pascal GOURAUD, Laurent FAVENNEC
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Publication number: 20220028725Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.Type: ApplicationFiled: October 7, 2021Publication date: January 27, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Pascal GOURAUD, Delia RISTOIU
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Patent number: 11171034Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.Type: GrantFiled: December 9, 2019Date of Patent: November 9, 2021Assignee: STMicroelectronics (Crolles 2) SASInventors: Pascal Gouraud, Delia Ristoiu
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Publication number: 20200203211Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.Type: ApplicationFiled: December 9, 2019Publication date: June 25, 2020Applicant: STMicroelectronics (Crolles 2) SASInventors: Pascal GOURAUD, Delia RISTOIU
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Publication number: 20120225560Abstract: The disclosure relates to a method for etching a target layer, comprising: depositing a hard mask layer onto a target layer and onto the hard mask layer, a first photosensitive layer, exposing the first photosensitive layer through a first mask to transfer first patterns into the photosensitive layer, transferring the first patterns into the hard mask layer, depositing onto the hard mask layer etched a second photosensitive layer, exposing the second photosensitive layer through a second mask to transfer second patterns into the second photosensitive layer, transferring the second patterns into the hard mask layer by etching this layer, and transferring the first and second patterns into the target layer through the hard mask, the second patterns forming lines, and the first patterns forming trenches cutting the lines in the hard mask.Type: ApplicationFiled: March 2, 2012Publication date: September 6, 2012Applicant: STMICROELECTRONICS (CROLLES 2) SASInventors: Pascal Gouraud, Bertrand Le-Gratiet