Abstract: A parallel to serial conversion circuit is disclosed. The circuit is used for converting parallel bits representing a plurality of words into serial bits. The circuit consists of storing means which comprises a plurality of word locations for temporarily storing the plurality of words at a parallel clock rate, and serialization means connected to the storing means for converting the parallel bits into serial bits at a serial clock rate. Each of the plurality of word locations is organized as a plurality of cells for storing each, one bit. Moreover the serialization means comprises parallel pointing means connected to the storing means for pointing to the plurality of words locations synchronously to the parallel clock, and serial pointing means also connected to the storing means for pointing to the plurality of cells synchronously to the serial clock.