Abstract: Device for compensating a DC component inherent in any radio frequency chain in which from a single measurement, generally obtained from a digital stage, a set of multiple compensation values is determined by a compensation value vector generating module and which compensation values are applied to multiple compensation points of the analog chain. The compensation values are calculated by an iterative process converging toward cancellation of the DC component and avoid saturating amplification components and components of the analog-to-digital converter. The module includes compensation value calculation units each configured to calculate a respective compensation value and provide the calculated compensation value to the respective compensation point.

Abstract: A procedure for compensating the DC component inherent in any radio frequency chain making it possible from a single measurement, generally located in the digital stage, to determine a set of multiple compensation values that must be applied to multiple compensation points of the analogue chain. The compensation values are calculated by an iterative process converging towards a cancellation of the DC component and avoid saturating amplification components and components of the analogue digital converter.

Abstract: The invention offers a procedure for compensating the DC component inherent in any radio frequency chain making it possible from a single measurement, generally located in the digital stage, to determine a set of multiple compensation values that must be applied to multiple compensation points of the analogue chain. The compensation values are calculated by an iterative process converging towards a cancellation of the DC component and avoid saturating amplification components and components of the analogue digital converter.

Abstract: The device (10) for digital demodulation comprises a polyphase filter (14) comprising a set of N distinct elementary digital filters and means (16) of selection, for each block of an elementary digital filter (Hi). It comprises a decimating stage (18) for selecting samples in each block on completion of the digital filtering and means (20) for determining samples to be selected comprising means (28) for computing an error signal for each filtered block and means (31) for evaluating the error signal suitable for determining the samples to be selected in the relevant block. That the means (16) of selection of an elementary digital filter (Hi) comprise means (28) for calculating an error signal. The means (28) for calculating an error signal are common to the means (16) of selection of the elementary digital filter (Hi) to be implemented and to the means (20) for determining samples to be selected. Application to a mobile telephone or base station.

Abstract: The device (10) for digital demodulation comprises a polyphase filter (14) comprising a set of N distinct elementary digital filters (Hi) and means (16) of selection, for each block of an elementary digital filter (Hi). These latter comprise means (28) for computing an error signal, means (30) for comparing performance indicators for the digital filters arising from the error signals and means (30) for determining the elementary digital filter (Hi) to be implemented in respect of the following block as a function of the result of the comparison. The digital filters (Hi) are ordered. They are chosen according to the order of the filters, as a function of the result of the comparison performed on the performance indicators for the elementary digital filters (Hi) implemented in respect of at least one previous block. Application to a mobile telephone or base station.

Abstract: The device (10) for digital demodulation comprises a polyphase filter (14) comprising a set of N distinct elementary digital filters and means (16) of selection, for each block of an elementary digital filter (Hi).

Abstract: The device (10) for digital demodulation comprises a polyphase filter (14) comprising a set of N distinct elementary digital filters (Hi) and means (16) of selection, for each block of an elementary digital filter (Hi). These latter comprise means (28) for computing an error signal, means (30) for comparing performance indicators for the digital filters arising from the error signals and means (30) for determining the elementary digital filter (Hi) to be implemented in respect of the following block as a function of the result of the comparison.