Abstract: A multiport series memory component for a multiprocessor system comprising an integrated circuit having a random access memory of a predetermined width corresponding to a block of information, an assembly of shift registers each of which has a size corresponding to the width of the memory unit, an internal parallel bus connecting the access of the memory unit to the shift registers, a shift register slection logic for validating the link on the internal bus between the memory unit and a predetermined shift register, and an assembly of extrnal input/output pins for the input of addresses to the memory unit for the input and validation of transfer commands in reading and writing of a block of information between the memory unit and the shift registers, for the input of a clock signal to each shift register, for bit-by-bit input of a block of information to each shift register and for the bit by bit output of a block of information from each shift register.