Abstract: The present invention relates to a method for generating a scan chain in a custom electronic circuit design with a plurality of storage elements. Said method comprises the steps of providing a schematic, propagating all scan inputs and all scan outputs of the storage elements to a top level of the design hierarchy, and declaring each scan input and each scan output on the top level as primary input and primary output, respectively. Said method comprises further the steps of adjusting a layout of the custom circuit according to the schematic, building up the scan chain according to a predetermined algorithm, and annotating the scan chain back into the schematic.

Abstract: A domino read bit line structure (20) integral to an SRAM array (1, 2) with thirty-two word lines or less to access SRAM cells divided into two groups (3, 4, 90, 100) is described. The bit line structure (20) includes a dynamic bit decode multiplexer (11, 40) and two NAND circuits (5, 80) used to combine the two groups (3, 4, 90, 100), wherein in order to reduce power consumption the two NANDS (80) drive the dynamic bit decode multiplexer (40) directly, such that true and complement dynamic outputs (rt, rc) drive a set-reset latch (50) to convert the dynamic outputs (rt, rc) to a single static signal (doc), wherein the output of the set-reset latch (50) is already static so that the set-reset latch (50) acts as an effective array output latch (7).

Abstract: A Tri-State circuit element (100) composed of Complementary Metal Oxide Semiconductor (CMOS)—devices is described. Said Tri-State circuit element (100) having a data signal input terminal (102) for receiving a data signal, an enable signal input terminal (104) for receiving an enable signal, and an output signal terminal (106) for providing an output signal. Furthermore a Tri-State-Multiplexer circuitry (300) composed of such Tri-State circuit elements (100) is described.

Abstract: The present invention relates to a scan chain and related cell design structures in a custom electronic circuit design with a plurality of storage elements. All scan inputs and all scan outputs of the storage elements are propagated to a top level of the design hierarchy in design. Each scan input and each scan output on the top level is declared a primary input and primary output, respectively. Propagating all the inputs and outputs of the storage elements to this level improves the wireability of the scan chain.

Abstract: A computer-implemented method and program product of modifying and presenting document data (150). Sub-elements (180) of document elements (TA) are marked as “fixed” elements. When the document data is presented in a visible document area of a computer program processing the document, the fixed elements are presented as long as their associated document elements are presented at least partially. An example for a document element is a table (TA), and its sub-elements can be table headers (180), table rows, and table columns. The associated data used for the presentation are called sliding table headers (430), sliding rows, and sliding columns.