Patents by Inventor Pascale Francis

Pascale Francis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PINNED PHOTODIODE PIXEL
    Publication number: 20240136372
    Abstract: A pixel for an ambient light and/or color sensor includes a plurality of pinned photodiodes. The pixel also includes a floating diffusion region. A ratio of an active area of the plurality of pinned photodiodes to an area of the floating diffusion region is greater than 150.
    Type: Application
    Filed: February 22, 2022
    Publication date: April 25, 2024
    Inventors: Benjamin Joseph SHEAHAN, Jong Mun PARK, Robert VAN ZEELAND, Kirk David PETERSON, Wern Ming KOE, George Richard KELLY, Mario MANNINGER, Dong-Long LIN, Pascale FRANCIS, Koen RUYTHOOREN
  • Method of forming a varactor with an increased linear tuning range
    Patent number: 7067384
    Abstract: The linear tuning range of a semiconductor varactor is substantially increased by forming a lightly-doped drain region of a first conductivity type in a semiconductor material of a second conductivity type between a heavily-doped diffusion of the second conductivity type and a lower-plate region of the semiconductor material.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: June 27, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Pascale Francis, Peter J. Hopper
  • Varactor and method of forming a varactor with an increased linear tuning range
    Patent number: 6653716
    Abstract: The linear tuning range of a semiconductor varactor is substantially increased by forming a lightly-doped drain region of a first conductivity type in a semiconductor material of a second conductivity type between a heavily-doped diffusion of the second conductivity type and a lower-plate region of the semiconductor material.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: November 25, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Pascale Francis, Peter J. Hopper
  • Compact non-volatile memory device and memory array
    Patent number: 6414872
    Abstract: A compact non-volatile memory device and memory array that are compatible with conventional MOS device processing. The compact non-volatile memory device includes a PMOS storage transistor with a floating gate in series with a PMOS access transistor. Since both of these PMOS transistors can be disposed in a single N-type well region, the size of the compact non-volatile memory device is relatively small. Another MOS processing compatible compact non-volatile memory device is formed in a semiconductor substrate of a first conductivity type (typically P-type) that includes a well region of a second conductivity type (typically N-type). Such a device also includes first source and drain regions of the first conductivity type, a first channel region defined therebetween, and a floating gate. This device also includes second source and drain regions of the first conductivity type, a second channel region defined therebetween, and a gate.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: July 2, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Albert Bergemont, Pascale Francis