Abstract: A processing device includes an array of processing elements, each processing element including an arithmetic logic unit to perform an operation. The processing device further includes interconnections among the array of processing elements to provide direct communication among neighboring processing elements of the array of processing elements. A processing element of the array of processing elements may be connected to a first neighbor processing element that is immediately adjacent the processing element. The processing element may be further connected to a second neighbor processing element that is immediately adjacent the first neighbor processing element. A processing element of the array of processing elements may be connected to a neighbor processing element via an input selector to selectively take output of the neighbor processing element as input to the processing element. A computing device may include such processing devices in an arrangement of banks.

Abstract: A unique method for chroma vertical upsampling used, for example, for conversion of the “4:2:0” format chroma information used in many applications of digital video, to the “4:2:2” or “4:4:4” format, is presented. This conversion is required so that video encoders can effect the display of this chroma information with a minimum of visible artifacts. The present invention carries out chroma vertical upsampling on a pixel by pixel basis. This chroma vertical upsampling is performed as a function of the amount of motion associated with each pixel as detected between 2 or more fields, and the field, frame and progressive sequence characteristics of the incoming video signal data.

Abstract: A unique method for chroma vertical upsampling used, for example, for conversion of the “4:2:0” format chroma information used in many applications of digital video, to the “4:2:2” or “4:4:4” format, is presented. This conversion is required so that video encoders can effect the display of this chroma information with a minimum of visible artifacts. The present invention carries out chroma vertical upsampling on a pixel by pixel basis. This chroma vertical upsampling is performed as a function of the amount of motion associated with each pixel as detected between 2 or more fields, and the field, frame and progressive sequence characteristics of the incoming video signal data.

Abstract: A unique method for chroma vertical upsampling used, for example, for conversion of the “4:2:0” format chroma information used in many applications of digital video, to the “4:2:2” or “4:4:4” format, is presented. This conversion is required so that video encoders can effect the display of this chroma information with a minimum of visible artifacts. The present invention carries out chroma vertical upsampling on a pixel by pixel basis. This chroma vertical upsampling is performed as a function of the amount of motion associated with each pixel as detected between 2 or more fields, and the field, frame and progressive sequence characteristics of the incoming video signal data.

Abstract: A software/hardware hybrid video decoder, particularly suited for decoding MPEG video, that takes advantage of processing capabilities of graphics coprocessors to perform the motion compensation portion of video decoding. Motion compensation is performed by bit block transfer (bit BLT) operations on the graphics coprocessor. The bit BLT operations perform the addition of pixels in the reference and error blocks. Bit BLT operations may also be used for interpolation between reference blocks to provide subpixel resolution for motion vectors.

Abstract: A unique method for chroma vertical upsampling used, for example, for conversion of the “4:2:0” format chroma information used in many applications of digital video, to the “4:2:2” or “4:4:4” format, is presented. This conversion is required so that video encoders can effect the display of this chroma information with a minimum of visible artifacts. The present invention carries out chroma vertical upsampling on a pixel by pixel basis. This chroma vertical upsampling is performed as a function of the amount of motion associated with each pixel as detected between 2 or more fields, and the field, frame and progressive sequence characteristics of the incoming video signal data.

Abstract: The present invention relates to a method of aligning and blending input digital samples, comprised of delaying the input samples by a clock pulse, to provide delayed data samples, subtracting a smaller fractional part from a larger fractional part of either an input sample number and a requested sample number to provide a sample difference number first factor, subtracting the sample difference number from 1 to provide a second factor, multiplying either of the input samples or the delayed samples by the first factor to provide a first result, multiplying the other of the input samples or the delayed samples by the second factor to provide a second result, and adding the results to provide output samples.

Abstract: A simplified fast maximum likelihood decoder for (1-D) channels comprising a first stage decoder for detecting possible charge violations in a threshold decoded input signal, a second stage decoder for resolving charge violations detected in the first stage decoder by finding the most likely data pattern consistent with the charge constraint of the input signal, and an output shift register for generating corrected estimated decoded data in response to receiving control signals output from the second stage decoder.