Patents by Inventor Pat Wang

Pat Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11687264
    Abstract: Technologies for an accelerator interface over Ethernet are disclosed. In the illustrative embodiment, a network interface controller of a compute device may receive a data packet. If the network interface controller determines that the data packet should be pre-processed (e.g., decrypted) with a remote accelerator device, the network interface controller may encapsulate the data packet in an encapsulating network packet and send the encapsulating network packet to a remote accelerator device on a remote compute device. The remote accelerator device may pre-process the data packet (e.g., decrypt the data packet) and send it back to the network interface controller. The network interface controller may then send the pre-processed packet to a processor of the compute device.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 27, 2023
    Assignee: Intel Corporation
    Inventors: Chih-Jen Chang, Brad Burres, Jose Niell, Dan Biederman, Robert Cone, Pat Wang, Kenneth Keels, Patrick Fleming
  • Publication number: 20220271855
    Abstract: Optical and electrical modules with enhanced features and associated apparatus and methods. The optical modules are configured to implement one or more features that are offloaded from Ethernet devices to which the optical modules are configured to be attached. The features include support for timestamping packets and preamble using IEEE 1588 Precision Time Protocol (PTP) profiles, support for implementing IEEE 1588 one-step operations, support for implementing IEEE 1588 Ethernet Synchronous Clocks (SyncE) profiles, support for In-Band Network Telemetry (INT), and support for implementing a MACsec security protocol defined by IEEE standard 802.1AD. The enhanced features provided by the optical modules enable Ethernet devices to be upgraded to support the enhanced features by replacing conventional optical modules with the optical modules disclosed herein. Support for White Rabbit IEEE PTP and SyncE profiles is also provided.
    Type: Application
    Filed: February 9, 2022
    Publication date: August 25, 2022
    Inventors: Daniel Christian BIEDERMAN, Pat WANG, Mark BORDOGNA, Raghuram NARAYAN, Renuka SAPKAL
  • Patent number: 10268464
    Abstract: Technologies for network application programming include a computing device that analyzes a network application source program. The source program includes a declarative description of a network application in a domain-specific language, such as P4. The computing device translates the declarative description of the network application into a register-transfer level (RTL) description, and then compiles the RTL description into a bitstream definition that is targeted to an FPGA. For example, the computing device may generate a parse graph based on the network application source program, and then generate an RTL TCAM-SRAM structure for each node of the parse graph. The computing device may optimize the RTL description, for example by simplifying RTL structures or removing unused logic. The computing device may program an FPGA with the bitstream definition. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Daniel P. Daly, Thomas E. Willis, Pat Wang, Vishal Anand, Hung Nguyen, Varsha Apte
  • Publication number: 20190012156
    Abstract: Technologies for network application programming include a computing device that analyzes a network application source program. The source program includes a declarative description of a network application in a domain-specific language, such as P4. The computing device translates the declarative description of the network application into a register-transfer level (RTL) description, and then compiles the RTL description into a bitstream definition that is targeted to an FPGA. For example, the computing device may generate a parse graph based on the network application source program, and then generate an RTL TCAM-SRAM structure for each node of the parse graph. The computing device may optimize the RTL description, for example by simplifying RTL structures or removing unused logic. The computing device may program an FPGA with the bitstream definition. Other embodiments are described and claimed.
    Type: Application
    Filed: July 7, 2017
    Publication date: January 10, 2019
    Inventors: Daniel P. Daly, Thomas E. Willis, Pat Wang, Vishal Anand, Hung Nguyen, Varsha Apte
  • Publication number: 20180152317
    Abstract: Technologies for an accelerator interface over Ethernet are disclosed. In the illustrative embodiment, a network interface controller of a compute device may receive a data packet. If the network interface controller determines that the data packet should be pre-processed (e.g., decrypted) with a remote accelerator device, the network interface controller may encapsulate the data packet in an encapsulating network packet and send the encapsulating network packet to a remote accelerator device on a remote compute device. The remote accelerator device may pre-process the data packet (e.g., decrypt the data packet) and send it back to the network interface controller. The network interface controller may then send the pre-processed packet to a processor of the compute device.
    Type: Application
    Filed: September 29, 2017
    Publication date: May 31, 2018
    Inventors: Chih-Jen Chang, Brad Burres, Jose Niell, Dan Biederman, Robert Cone, Pat Wang, Kenneth Keels, Patrick Fleming