Patents by Inventor Patrice M. Parris
Patrice M. Parris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9741793Abstract: An electronic apparatus includes a semiconductor substrate and first and second transistors disposed in the semiconductor substrate. The first transistor includes a channel region and a drain region adjacent the channel region. The second transistor includes a channel region, a false drain region adjacent the channel region, and a drain region electrically coupled to the channel region by a drift region such that the second transistor is configured for operation at a higher voltage level than the first transistor. The respective channel regions of the first and second transistors have a common configuration characteristic.Type: GrantFiled: April 16, 2012Date of Patent: August 22, 2017Assignee: NXP USA, INC.Inventors: Patrice M. Parris, Weize Chen
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Patent number: 9704853Abstract: Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within a portion of the substrate contained by the isolation structure, and a resistor circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region, which is separated from the isolation structure by a portion of the semiconductor substrate having the first conductivity type. The resistor circuit is connected between the isolation structure and the body region. The resistor circuit may include one or more resistor networks and, optionally, a Schottky diode and/or one or more PN diode(s) in series and/or parallel with the resistor network(s).Type: GrantFiled: November 7, 2012Date of Patent: July 11, 2017Assignee: NXP USA, INC.Inventors: Hubert M. Bode, Weize Chen, Richard J. De Souza, Patrice M. Parris
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Patent number: 9673188Abstract: A method of fabricating a laterally diffused metal-oxide-semiconductor (LDMOS) transistor device having a bipolar transistor for electrostatic discharge (ESD) protection includes doping a substrate to form a body region of the LDMOS transistor device in the substrate, the body region having a first conductivity type, forming a doped isolating region of the LDMOS transistor device in the substrate, the doped isolating region having a second conductivity type and surrounding a device area of the LDMOS transistor device in which the body region is disposed, forming a base contact region of the bipolar transistor, the base contact region being disposed within the body region and having the first conductivity type, and doping the substrate to form an isolation contact region for the doped isolating region that defines a collector region of the bipolar transistor, to form source and drain regions of the LDMOS transistor device in the substrate, and to form an emitter region of the bipolar transistor within the bodyType: GrantFiled: December 11, 2015Date of Patent: June 6, 2017Assignee: NXP USA, INC.Inventors: Weize Chen, Patrice M. Parris
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Publication number: 20170146485Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.Type: ApplicationFiled: February 8, 2017Publication date: May 25, 2017Inventors: Patrice M. Parris, Weize Chen, Richard J. De Souza, Md M. Hoque, John M. McKenna
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Patent number: 9620496Abstract: Protection circuits, device structures and related fabrication methods are provided. An exemplary protection circuit includes a first protection arrangement and a second protection arrangement. The first protection arrangement includes a first transistor having a first collector, a first emitter, and a first base coupled to the first emitter at a first node, and a second transistor having a second collector, a second emitter, and a second base coupled to the second emitter at a second node, the second collector being coupled to the first collector at a third node. The second protection arrangement is coupled electrically in series between the second node and a fourth node. The protection circuit further includes a first diode coupled between the third node and the fourth node.Type: GrantFiled: March 10, 2015Date of Patent: April 11, 2017Assignee: NXP USA, INC.Inventors: Weize Chen, Hubert M. Bode, Andreas Laudenbach, Kurt U. Neugebauer, Patrice M. Parris
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Publication number: 20170092760Abstract: A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.Type: ApplicationFiled: December 14, 2016Publication date: March 30, 2017Inventors: Patrice M. Parris, Hubert M. Bode, Weize Chen, Richard J. DeSouza, Andreas Laudenbach, Kurt U. Neugebauer
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Patent number: 9607981Abstract: Embodiments include methods of forming a semiconductor device having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a source region of the first conductivity type, and the diode circuit is connected between the isolation structure and the source region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).Type: GrantFiled: August 17, 2015Date of Patent: March 28, 2017Assignee: NXP USA, INC.Inventors: Weize Chen, Hubert M. Bode, Richard J. De Souza, Patrice M. Parris
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Patent number: 9599587Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.Type: GrantFiled: September 5, 2014Date of Patent: March 21, 2017Assignee: NXP USA, INC.Inventors: Patrice M. Parris, Weize Chen, Richard J. De Souza, Md M. Hoque, John M. McKenna
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Patent number: 9570440Abstract: Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region of the second conductivity type, and the diode circuit is connected between the isolation structure and the body region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).Type: GrantFiled: September 21, 2015Date of Patent: February 14, 2017Assignee: NXP USA, Inc.Inventors: Weize Chen, Hubert M. Bode, Richard J. De Souza, Patrice M. Parris
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Patent number: 9559097Abstract: A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.Type: GrantFiled: October 6, 2014Date of Patent: January 31, 2017Assignee: NXP USA, Inc.Inventors: Patrice M. Parris, Hubert M. Bode, Weize Chen, Richard J DeSouza, Andreas Laudenbach, Kurt U. Neugebauer
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Patent number: 9553187Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a body well region having a first conductivity type, a drift region and a source region each having a second conductivity type, where a channel portion of the body well region resides laterally between the source region and a first portion of the drift region that is adjacent to the channel portion. A gate structure overlies the channel portion and the adjacent portion of the drift region. A portion of the gate structure overlying the channel portion proximate the source region has the second conductivity type. Another portion of the gate structure that overlies the adjacent portion of the drift region has a different doping, and overlaps at least a portion of the channel portion, with the threshold voltage associated with the gate structure being influenced by the amount of overlap.Type: GrantFiled: December 11, 2014Date of Patent: January 24, 2017Assignee: NXP USA, Inc.Inventors: Weize Chen, Richard J. De Souza, Mazhar Ul Hoque, Patrice M. Parris
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Patent number: 9541521Abstract: A mechanism is provided for enhancing the sensitivity of an ion-sensitive semiconductor device by creating a second gate coupled to a sense plate that can improve the amount of charge brought to the ion-sensitive semiconductor device conductivity modulated region (e.g., a channel region of an ISFET). This is accomplished by utilizing a buried dielectric layer associated with the ion-sensitive semiconductor device conductivity modulated region as the second gate dielectric. The buried dielectric layer is coupled to the sense plate using an isolated well region as a conductor that is coupled to metal layers extending to the sense plate. Some embodiments further use the buried dielectric layer as the sole gate dielectric for the semiconductor device, thereby allowing the traditional gate dielectric region to be coupled to a protection diode. This protection diode then protects the gate dielectric from plasma induced damage and electrostatic discharge.Type: GrantFiled: October 30, 2015Date of Patent: January 10, 2017Assignee: NXP USA, Inc.Inventors: Md M. Hoque, Weize Chen, Patrice M. Parris
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Patent number: 9537000Abstract: A semiconductor device includes a substrate having a surface, a composite body region disposed in the substrate, having a first conductivity type, and comprising a body contact region at the surface of the substrate and a well in which a channel is formed during operation, a source region disposed in the semiconductor substrate adjacent the composite body region and having a second conductivity type, and an isolation region disposed between the body contact region and the source region. The composite body region further includes a body conduction path region contiguous with and under the source region, and the body conduction path region has a higher dopant concentration level than the well.Type: GrantFiled: March 11, 2013Date of Patent: January 3, 2017Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Weize Chen, Patrice M. Parris
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Publication number: 20160370314Abstract: Protected sensor field effect transistors (SFETs). The SFETs include a semiconductor substrate, a field effect transistor, and a sense electrode. The SFETs further include an analyte-receiving region that is supported by the semiconductor substrate, is in contact with the sense electrode, and is configured to receive an analyte fluid. The analyte-receiving region is at least partially enclosed. In some embodiments, the analyte-receiving region can be an enclosed analyte channel that extends between an analyte inlet and an analyte outlet. In these embodiments, the enclosed analyte channel extends such that the analyte inlet and the analyte outlet are spaced apart from the sense electrode. In some embodiments, the SFETs include a cover structure that at least partially encloses the analyte-receiving region and is formed from a cover material that is soluble within the analyte fluid. The methods include methods of manufacturing the SFETs.Type: ApplicationFiled: August 30, 2016Publication date: December 22, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Patrice M. Parris, Weize Chen, Richard J. de Souza, Jose Fernandez Villasenor, Md M. Hoque, David E. Niewolny, Raymond M. Roop
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Publication number: 20160365422Abstract: Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.Type: ApplicationFiled: August 24, 2016Publication date: December 15, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Weize Chen, Richard J. de Souza, Md M. Hoque, Patrice M. Parris
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Publication number: 20160356740Abstract: Protected sensor field effect transistors (SFETs). The SFETs include a semiconductor substrate, a field effect transistor, and a sense electrode. The SFETs further include an analyte-receiving region that is supported by the semiconductor substrate, is in contact with the sense electrode, and is configured to receive an analyte fluid. The analyte-receiving region is at least partially enclosed. In some embodiments, the analyte-receiving region can be an enclosed analyte channel that extends between an analyte inlet and an analyte outlet. In these embodiments, the enclosed analyte channel extends such that the analyte inlet and the analyte outlet are spaced apart from the sense electrode. In some embodiments, the SFETs include a cover structure that at least partially encloses the analyte-receiving region and is formed from a cover material that is soluble within the analyte fluid. The methods include methods of manufacturing the SFETs.Type: ApplicationFiled: June 5, 2015Publication date: December 8, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Patrice M. Parris, Weize Chen, Richard J. de Souza, Jose Fernandez Villasenor, Md M. Hoque, David E. Niewolny, Raymond M. Roop
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Patent number: 9502304Abstract: Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a drain region of the second conductivity type, and the diode circuit is connected between the isolation structure and the drain region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).Type: GrantFiled: September 4, 2015Date of Patent: November 22, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Weize Chen, Hubert M. Bode, Richard J. De Souza, Patrice M. Parris
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Patent number: 9494550Abstract: Protected sensor field effect transistors (SFETs). The SFETs include a semiconductor substrate, a field effect transistor, and a sense electrode. The SFETs further include an analyte-receiving region that is supported by the semiconductor substrate, is in contact with the sense electrode, and is configured to receive an analyte fluid. The analyte-receiving region is at least partially enclosed. In some embodiments, the analyte-receiving region can be an enclosed analyte channel that extends between an analyte inlet and an analyte outlet. In these embodiments, the enclosed analyte channel extends such that the analyte inlet and the analyte outlet are spaced apart from the sense electrode. In some embodiments, the SFETs include a cover structure that at least partially encloses the analyte-receiving region and is formed from a cover material that is soluble within the analyte fluid. The methods include methods of manufacturing the SFETs.Type: GrantFiled: June 5, 2015Date of Patent: November 15, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Patrice M. Parris, Weize Chen, Richard J. de Souza, Jose Fernandez Villasenor, Md M. Hoque, David E. Niewolny, Raymond M. Roop
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Patent number: 9478467Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary fabrication method involves forming a layer of gate electrode material overlying a semiconductor substrate, forming a layer of masking material overlying the gate electrode material, and patterning the layer of masking material to define a channel region within a well region in the semiconductor substrate that underlies the gate electrode material. Prior to removing the patterned layer of masking material, the fabrication process etches the layer of gate electrode material to form a gate structure overlying the channel region using the patterned layer of masking material as an etch mask and forms extension regions in the well region using the patterned layer of masking material as an implant mask. Thereafter, the patterned layer of masking material is removed after forming the gate structure and the extension regions.Type: GrantFiled: November 17, 2014Date of Patent: October 25, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Weize Chen, Richard J. De Souza, Patrice M. Parris
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Patent number: 9466608Abstract: A method for making a semiconductor structure includes forming an oxide layer onto non-volatile memory, high, and low voltage device regions of a substrate and forming a first gate material layer over the oxide layer. The first gate material layer is patterned to form a set of memory device select gates in the non-volatile memory device region and a set of gates in the high voltage device region. The patterning is performed while maintaining the oxide and first gate material layers over the low voltage device region. The method also includes forming a second gate material layer over the structure and forming a non-volatile storage layer between the set of select gates and the second gate material layer, from which a set of memory device control gates is patterned. Thereafter, the first gate material layer is patterned to form a set of gates in the low voltage device region.Type: GrantFiled: October 28, 2015Date of Patent: October 11, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Weize Chen, Richard J De Souza, Patrice M Parris