Abstract: A system for implementing waveform processing in a software defined radio (SDR) includes a scaleable array processor having a plurality of micro-engines (MEs) interconnected by a two dimensional topology. Each micro-engine includes multiple FIFOs for interconnecting to each other in the two dimensional topology. One micro-engine communicates with another adjacent micro-engine by way of the respective FIFOs. The micro-engines are dedicated to predetermined algorithms. The two dimensional topology includes an array of N×M micro-engines interconnected by the multiple FIFOs. The N×M are integer numbers of rows and columns, respectively, in the array of micro-engines. The micro-engines are dedicated to baseband processing of data for RF transmission or RF reception.

Abstract: A circuit is provided for transferring a signal from a fast clock domain to a slow clock domain. The circuit includes a fast clock domain configured to receive an input signal and, responsively, transfer an intermediate signal. The circuit also a slow clock domain configured to receive the transferred intermediate signal from the fast clock domain and, responsively, generate an output signal. The circuit further includes a first synchronizer disposed in the slow clock domain and a second synchronizer disposed in the fast clock domain. The first synchronizer, operating with a slow clock, is configured to receive the intermediate signal and, responsively, provide the output signal as a transferred signal which is synchronized to the input signal. The second synchronizer, operating with a fast clock, is configured to receive a feedback signal from the first synchronizer for acknowledging synchronization of the output signal to the input signal.

Abstract: An RFIC controller configured for executing multiple tasks. A serial interface is included having a serial bus for receiving a data stream having control bits and data bits. One or more registers are coupled to the serial bus for storing the control bits and data bits as they are received. Control circuitry is also included. The data stream is formatted such that the control bits are received before the data bits, the control bits specifying an operation. The control circuitry is configured to examine the control bits as they are received to determine the operation specified by the control bits before the data bits are received. A task corresponding to the operation specified by the control bits is then initiated before the data bits are received.

Abstract: An RFIC controller configured for executing multiple tasks. A serial interface is included having a serial bus for receiving a data stream having control bits and data bits. One or more registers are coupled to the serial bus for storing the control bits and data bits as they are received. Control circuitry is also included. The data stream is formatted such that the control bits are received before the data bits, the control bits specifying an operation. The control circuitry is configured to examine the control bits as they are received to determine the operation specified by the control bits before the data bits are received. A task corresponding to the operation specified by the control bits is then initiated before the data bits are received.