Patents by Inventor Patrick Caffrey

Patrick Caffrey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11781638
    Abstract: An axle assembly for a working machine is provided. The axle assembly has an axle housing comprising a central portion housing a gear, wherein the gear is configured to rotate about an axis and is configured to be partially disposed in a lubricant reservoir, and at least one arm portion extending from the central portion, with the arm portion housing at least one driveshaft. The axle assembly further includes a conduit assembly configured to direct lubricant from the central portion to the arm portion, with the conduit assembly including a lubricant catcher having an inlet disposed in an interior volume of the central portion.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: October 10, 2023
    Assignee: J. C. Bamford Excavators Limited
    Inventors: Thomas Deckland Hurd, John Gwynfor Lloyd, Jonathan Francis Nelson, Patrick Caffrey, Gareth Trimmer
  • Publication number: 20220324256
    Abstract: An axle assembly for a working machine is provided. The axle assembly has an axle housing comprising a central portion housing a gear, wherein the gear is configured to rotate about an axis and is configured to be partially disposed in a lubricant reservoir, and at least one arm portion extending from the central portion, with the arm portion housing at least one driveshaft. The axle assembly further includes a conduit assembly configured to direct lubricant from the central portion to the arm portion, with the conduit assembly including a lubricant catcher having an inlet disposed in an interior volume of the central portion.
    Type: Application
    Filed: April 12, 2022
    Publication date: October 13, 2022
    Applicant: J. C. Bamford Excavators Limited
    Inventors: Thomas Deckland Hurd, John Gwynfor Lloyd, Jonathan Francis Nelson, Patrick Caffrey, Gareth Trimmer
  • Patent number: 11068279
    Abstract: A method includes identifying a first distributed conversion and control assembly (DCCA) in a central electronics complex (CEC) of a computer system, the CEC containing the first DCCA and a second DCCA, each of the first DCCA and the second DCCA having a flexible service processor (FSP); determining that the computer system satisfies preconditions for concurrent replacement of the first DCCA; disabling control software for a thermal and power management device (TPMD) of the first DCCA; fencing off the first DCCA; depowering the first DCCA; receiving a new media access control (MAC) address of a replacement DCCA; reconfiguring an operating system of the CEC to recognize the new MAC address of the replacement DCCA; powering on the replacement DCCA; removing the fencing off of the first DCCA; and resetting an FSP of the replacement DCCA.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: July 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ronald P Corrado, Anthony Joseph Cozzolino, Gerald Fahr, Bret G Bidwell, Ellick Chi-lick Law, Patrick Caffrey, William Wajda
  • Publication number: 20200285484
    Abstract: A method includes identifying a first distributed conversion and control assembly (DCCA) in a central electronics complex (CEC) of a computer system, the CEC containing the first DCCA and a second DCCA, each of the first DCCA and the second DCCA having a flexible service processor (FSP); determining that the computer system satisfies preconditions for concurrent replacement of the first DCCA; disabling control software for a thermal and power management device (TPMD) of the first DCCA; fencing off the first DCCA; depowering the first DCCA; receiving a new media access control (MAC) address of a replacement DCCA; reconfiguring an operating system of the CEC to recognize the new MAC address of the replacement DCCA; powering on the replacement DCCA; removing the fencing off of the first DCCA; and resetting an FSP of the replacement DCCA.
    Type: Application
    Filed: February 28, 2020
    Publication date: September 10, 2020
    Inventors: Ronald P. Corrado, Anthony Joseph Cozzolino, Gerald Fahr, Bret G. Bidwell, Ellick Chi-lick Law, Patrick Caffrey, William Wajda
  • Patent number: 7810093
    Abstract: In a parallel computing environment comprising a network of SMP nodes each having at least one processor, a parallel-aware co-scheduling method and system for improving the performance and scalability of a dedicated parallel job having synchronizing collective operations. The method and system uses a global co-scheduler and an operating system kernel dispatcher adapted to coordinate interfering system and daemon activities on a node and across nodes to promote intra-node and inter-node overlap of said interfering system and daemon activities as well as intra-node and inter-node overlap of said synchronizing collective operations. In this manner, the impact of random short-lived interruptions, such as timer-decrement processing and periodic daemon activity, on synchronizing collective operations is minimized on large processor-count SPMD bulk-synchronous programming styles.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: October 5, 2010
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Terry R. Jones, Pythagoras C. Watson, William Tuel, Larry Brenner, Patrick Caffrey, Jeffrey Fier
  • Publication number: 20050131865
    Abstract: In a parallel computing environment comprising a network of SMP nodes each having at least one processor, a parallel-aware co-scheduling method and system for improving the performance and scalability of a dedicated parallel job having synchronizing collective operations. The method and system uses a global co-scheduler and an operating system kernel dispatcher adapted to coordinate interfering system and daemon activities on a node and across nodes to promote intra-node and inter-node overlap of said interfering system and daemon activities as well as intra-node and inter-node overlap of said synchronizing collective operations. In this manner, the impact of random short-lived interruptions, such as timer-decrement processing and periodic daemon activity, on synchronizing collective operations is minimized on large processor-count SPMD bulk-synchronous programming styles.
    Type: Application
    Filed: November 15, 2004
    Publication date: June 16, 2005
    Inventors: Terry Jones, Pythagoras Watson, William Tuel, Larry Brenner, Patrick Caffrey, Jeffrey Fier