Abstract: For use in a receiver capable of decoding trellis encoded signals, there is disclosed an apparatus and method for reducing error propagation in a decision feedback equalizer. The apparatus of the invention comprises a trellis decoder and a decision feedback equalizer coupled to the path memory outputs of the trellis decoder. The decision feedback equalizer is capable of obtaining symbol values from the trellis decoder and using the symbol values as estimates in channel equalization. In one embodiment of the invention, a first equalizer and trellis decoder combination is used to estimate a symbol stream. Then a second equalizer and trellis decoder combination is used to further minimize error by operating on the output of the first equalizer and trellis decoder combination.

Abstract: For use in a receiver capable of decoding trellis encoded signals, there is disclosed an apparatus and method for reducing error propagation in a decision feedback equalizer. The apparatus of the invention comprises a trellis decoder and a decision feedback equalizer coupled to the path memory outputs of the trellis decoder. The decision feedback equalizer is capable of obtaining symbol values from the trellis decoder and using the symbol values as estimates in channel equalization. In one embodiment of the invention, a first equalizer and trellis decoder combination is used to estimate a symbol stream. Then a second equalizer and trellis decoder combination is used to further minimize error by operating on the output of the first equalizer and trellis decoder combination.

Abstract: There is disclosed a digital filter cell capable of processing in a first mode a first signal having real data components only and processing in a second mode a second signal having real data components and imaginary data components. The digital filter cell comprises: 1) a plurality of serially coupled coefficient registers for receiving a sequence of coefficients; 2) a plurality of serially coupled data registers for receiving a sequence of digital data samples, each register having a tap output; 3) a data multiplexer having a plurality of input channels for receiving the tap outputs from the plurality of serially coupled data registers; and 4) a product summation circuit having a first input coupled to an output of the data multiplexer and a second input coupled to an output of a selected one of the plurality of serially coupled coefficient registers.