Patents by Inventor Patrick De Bakker
Patrick De Bakker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113924Abstract: An isolated gate driver includes a first input terminal to receive gate information and one or more input terminals to receive configuration information. A modulation circuit generates a modulated signal having four possible states, each of the four possible states corresponding to a different unique pair of values of the gate information and the configuration information. The modulation circuit represents two of the states using on-off keying (OOK) while the configuration information is at a first value and represents two of the states as a modification to the OOK modulation based on the configuration information being at a second value. The modulated signal is sent over an isolation communication channel coupling a transmitter and receiver of the isolated gate driver.Type: ApplicationFiled: December 12, 2023Publication date: April 4, 2024Inventors: Carlos Jesus Briseno-Vidrios, Michael R. May, Patrick De Bakker, Fernando Naim Lavalle Aviles
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Patent number: 11888658Abstract: An isolated gate driver includes a first input terminal to receive gate information and one or more input terminals to receive configuration information. A modulation circuit generates a modulated signal having four possible states, each of the four possible states corresponding to a different unique pair of values of the gate information and the configuration information. The modulation circuit represents two of the states using on-off keying (OOK) while the configuration information is at a first value and represents two of the states as a modification to the OOK modulation based on the configuration information being at a second value. The modulated signal is sent over an isolation communication channel coupling a transmitter and receiver of the isolated gate driver.Type: GrantFiled: October 8, 2020Date of Patent: January 30, 2024Assignee: Skyworks Solutions, Inc.Inventors: Carlos Jesus Briseno-Vidrios, Michael R. May, Patrick De Bakker, Fernando Naim Lavalle Aviles
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Patent number: 11641197Abstract: A method for protecting a system including a driver integrated circuit includes receiving a driver input signal. The method includes driving an output signal externally to the driver integrated circuit. The output signal is driven based on the driver input signal and an indication of a delay between receipt of an edge of the driver input signal and arrival of a corresponding edge of the output signal at an output node coupled to a terminal of the driver integrated circuit.Type: GrantFiled: April 28, 2021Date of Patent: May 2, 2023Assignee: Skyworks Solutions, Inc.Inventors: Péter Onódy, Tamás Marozsák, Michael R. May, Fernando Naim Lavalle Aviles, Patrick De Bakker
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Patent number: 11575305Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.Type: GrantFiled: October 8, 2020Date of Patent: February 7, 2023Assignee: Skyworks Solutions, Inc.Inventors: Michael R. May, Fernando Naim Lavalle Aviles, Carlos Jesus Briseno-Vidrios, Patrick De Bakker, Gabor Marek, Charles Guo Lin, Peter Onody, Tamás Marozsák, András V. Horváth
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Patent number: 11539559Abstract: An integrated circuit includes a demodulator to demodulate a signal simultaneously transmitted over an isolation communication channel and obtain gate information and configuration information. The demodulator includes a gate demodulation path and a configuration demodulation path. The received signal oscillates at a first frequency to represent a first state, oscillates at different frequencies to represent a seconds state, oscillates at a third frequency (or third and fourth frequencies), which are lower than the first frequency, to represent a third state, and the received signal is steady state to represent a fourth state. The gate demodulation path detects the first and second states. The configuration demodulation path includes first and second sub-demodulation paths. An envelope detector in the first sub-demodulation path detects the second state and the second sub-demodulation path detects the third state. The configuration demodulation paths uses an output of the gate demodulation path.Type: GrantFiled: October 8, 2020Date of Patent: December 27, 2022Assignee: Skyworks Solutions, Inc.Inventors: Carlos Jesus Briseno-Vidrios, Michael R. May, Patrick De Bakker
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Publication number: 20220352884Abstract: A method for protecting a system including a driver integrated circuit includes receiving a driver input signal. The method includes driving an output signal externally to the driver integrated circuit. The output signal is driven based on the driver input signal and an indication of a delay between receipt of an edge of the driver input signal and arrival of a corresponding edge of the output signal at an output node coupled to a terminal of the driver integrated circuit.Type: ApplicationFiled: April 28, 2021Publication date: November 3, 2022Inventors: Péter Onódy, Tamás Marozsák, Michael R. May, Fernando Naim Lavalle Aviles, Patrick De Bakker
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Publication number: 20220115941Abstract: An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.Type: ApplicationFiled: October 8, 2020Publication date: April 14, 2022Inventors: Michael R. May, Fernando Naim Lavalle Aviles, Carlos Jesus Briseno-Vidrios, Patrick De Bakker, Gabor Marek, Charles Guo Lin, Peter Onody, Tamás Marozsák, András V. Horváth
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Publication number: 20220116249Abstract: An isolated gate driver includes a first input terminal to receive gate information and one or more input terminals to receive configuration information. A modulation circuit generates a modulated signal having four possible states, each of the four possible states corresponding to a different unique pair of values of the gate information and the configuration information. The modulation circuit represents two of the states using on-off keying (OOK) while the configuration information is at a first value and represents two of the states as a modification to the OOK modulation based on the configuration information being at a second value. The modulated signal is sent over an isolation communication channel coupling a transmitter and receiver of the isolated gate driver.Type: ApplicationFiled: October 8, 2020Publication date: April 14, 2022Inventors: Carlos Jesus Briseno-Vidrios, Michael R. May, Patrick De Bakker, Fernando Naim Lavalle Aviles
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Publication number: 20220116250Abstract: An integrated circuit includes a demodulator to demodulate a signal simultaneously transmitted over an isolation communication channel and obtain gate information and configuration information. The demodulator includes a gate demodulation path and a configuration demodulation path. The received signal oscillates at a first frequency to represent a first state, oscillates at different frequencies to represent a seconds state, oscillates at a third frequency (or third and fourth frequencies), which are lower than the first frequency, to represent a third state, and the received signal is steady state to represent a fourth state. The gate demodulation path detects the first and second states. The configuration demodulation path includes first and second sub-demodulation paths. An envelope detector in the first sub-demodulation path detects the second state and the second sub-demodulation path detects the third state. The configuration demodulation paths uses an output of the gate demodulation path.Type: ApplicationFiled: October 8, 2020Publication date: April 14, 2022Inventors: Carlos Jesus Briseno-Vidrios, Michael R. May, Patrick De Bakker
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Patent number: 8020010Abstract: A memory power controller comprises a clock generation circuitry for generating a first clock signal and a second clock signal responsive to a source clock and a determination that the source clock has a period greater than a predetermined value. The first clock is generated responsive to a determination that the source clock has a period greater than the predetermined value and the second clock is generated responsive to the determination that the source clock has a period less than the predetermined value. Memory time-out circuitry generates a memory enable/disable signal to control operation of an associated memory responsive to the clock signal and the determination that the source clock has a period greater than the predetermined value. The memory time-out circuitry further synchronizes the memory enable/disable signal with the source clock.Type: GrantFiled: June 24, 2008Date of Patent: September 13, 2011Assignee: Silicon Laboratories Inc.Inventors: Douglas F. Pastorello, Patrick De Bakker, Louis J. Nervegna
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Publication number: 20090319814Abstract: A memory power controller comprises a clock generation circuitry for generating a first clock signal and a second clock signal responsive to a source clock and a determination that the source clock has a period greater than a predetermined value. The first clock is generated responsive to a determination that the source clock has a period greater than the predetermined value and the second clock is generated responsive to the determination that the source clock has a period less than the predetermined value. Memory time-out circuitry generates a memory enable/disable signal to control operation of an associated memory responsive to the clock signal and the determination that the source clock has a period greater than the predetermined value. The memory time-out circuitry further synchronizes the memory enable/disable signal with the source clock.Type: ApplicationFiled: June 24, 2008Publication date: December 24, 2009Applicant: SILICON LABORATORIES INC.Inventors: DOUGLAS F. PASTORELLO, PATRICK DE BAKKER, LOUIS J. NERVEGNA