Abstract: The present invention relates to a device for generating sound messages, comprising: a generation chain configured to generate a first and a second sound signal carrying a useful audio signal and a test audio signal; a conversion chain configured to transform the first and second sound signals into first and second analog signals; and a verification chain configured to extract the test audio signal from a combination of the analog signals to verify the integrity of the useful audio signal. The first sound signal corresponds to the sum of the test audio signal and the useful audio signal, and the second sound signal corresponds to the sum of the test audio signal and an opposite signal corresponding to the opposite of the useful audio signal.

Abstract: The present invention relates to a device for generating sound messages, comprising: a generation chain configured to generate a first and a second sound signal carrying a useful audio signal and a test audio signal; a conversion chain configured to transform the first and second sound signals into first and second analog signals; and a verification chain configured to extract the test audio signal from a combination of the analog signals to verify the integrity of the useful audio signal. The first sound signal corresponds to the sum of the test audio signal and the useful audio signal, and the second sound signal corresponds to the sum of the test audio signal and an opposite signal corresponding to the opposite of the useful audio signal.

Abstract: An electronic system for aeronautical applications, includes at least one electronic memory comprising a first plurality (T) of words and an error detection system for detecting errors in the words. The electronic system comprises an error counting device comprising: a register comprising a second plurality (NBR) of bits, an address of a bit being associated with at least one word; means for indexing the bit associated with the word when the error detection system flags an alteration of the word, the indexation of the bit being unique within a given time period, regardless of the number of times the alteration of the word is detected by the error detection system within this given time period; means for resetting the register at the end of the given time period.

Abstract: A triplication register device includes a first register, a second register and a third register, the three registers being identical and containing the same information in common use, a majority vote device and a self-correction device, the correction being dependent on the result from the majority vote device, each register being controlled by an output of a dual-input multiplexer (mux), the first input corresponding to a functional write operation, the second input corresponding to the result of the majority vote, wherein the triplication device comprises a test device whose function is to block, on command and independently, either the functional write operation to the first register, or the functional write operation to the second register, or the functional write operation to the third register, or the self-correction. The test device may comprise a control register that may also be secured by triplication.

Abstract: A method of ACM acquisition/confirmation of a plurality of logic signals SI(i) combines a loop for the single confirmation processing for all the sampled signals, with a sequential sampling of these signals. On each sampling, the confirmation loop processes the current sampled signal SI(i), in order to decide on the updating of an output register Qs(i) with the current sampled state Sk, depending on whether or not it is confirmed, either that this state is not to be confirmed, or that this state is to be confirmed, and that the associated confirmation duration ? has elapsed.

Abstract: A method of testing an electronic circuit having a plurality of data transfer operators operating on memory resources defining a shared memory space is described. According to at least one embodiment, the shared memory space is initialized by writing data items to the shared memory space, and each data item is unique in the shared memory space. All or some of the shared memory space is partitioned into a plurality of disjoint memory blocks, the memory blocks being organized into one or more groups of blocks, each memory block belongs to one of the groups, and all memory blocks of the same group have the same size. A test scenario comprising at least one data transfer operation is executed, and the content of the shared memory space is verified.

Abstract: A method of ACM acquisition/confirmation of a plurality of logic signals SI(i) combines a loop for the single confirmation processing for all the sampled signals, with a sequential sampling of these signals. On each sampling, the confirmation loop processes the current sampled signal SI(i), in order to decide on the updating of an output register Qs(i) with the current sampled state Sk, depending on whether or not it is confirmed, either that this state is not to be confirmed, or that this state is to be confirmed, and that the associated confirmation duration ? has elapsed.

Abstract: A method of testing a complex electronic circuit, comprising a plurality of transfer operators DMA—0, DMA—1, UDMA, Software routines executed by the processor, and a plurality of memory resources (M1, M2, M3, M4) forming a shared memory space 1 on which the various operators can work, comprises an initialization of each address of the memory space that is shared by a data item which is a bijective function of this address, a partitioning of this shared memory space 1 into a plurality of blocks 0, B1, B2, B3, B4, the blocks being grouped into at least one group G0, comprising only blocks of the same size, and an execution of a series of transfers S(T), each transfer being carried out by an operator, for transferring the content of a source block from a group, to a destination block of the same group.