Abstract: A compiler receives a graph describing a neural network and accesses data to describe a target computing device to implement the neural network. The compiler generates an intermediate representation from the graph and the data, and determines dependencies between operations identified in the intermediate representation. A set of barrier tasks are determined to be performed to control flow of the set of operations based on the dependencies, where the set of barrier tasks are to be performed using hardware barrier components on the target computing device. Indications of the barrier tasks are inserted into the intermediate representation. The compiler generates a binary executable from the intermediate representation to enable performance of the barrier tasks to control performance of the set of operations at the target computing device.

Abstract: A compiler receives a graph describing a neural network and accesses data to describe a target computing device to implement the neural network. The compiler generates an intermediate representation from the graph and the data, where the intermediate representation includes an operator model, a data model, and a control model. The compiler generates a binary executable using each of the operator model, data model, and control model of the intermediate representation.

Abstract: A codec to compress information by generating a set of basis vectors based upon a population of vectors according to a pseudo-random sequence; and encoding the information into a set of coefficients indicative of a projection of the information onto the linear span of the set of basis vectors provided the projection satisfies a criterion of goodness. The generation of the basis vectors is based upon a genetic algorithm. To decode, the information is reconstructed or uncompressed by summing the set of basis vectors weighted by the set of coefficients.

Abstract: A programmable and testable memory address decoder for a computer system where a static random access memory device is used to store memory configuration information. The computer system includes a processor which is coupled to the memory address decoder via data and address lines. The memory address decoder includes an SRAM for storing a memory map which associates memory attributes with memory ranges or blocks of memory. The memory attributes include: memory residence, caching, write protection of memory ranges, and the decoding of other memory modules. The present invention also includes control logic, a read-back register, and a mode register for controlling the loading and read back verification of the SRAM. The control logic operates the memory address decoder in one of four modes. These modes include: 1) power-up mode, 2) programming mode, 3) read back mode, and 4) normal operation mode. One of these modes is selected by loading the mode register with a value corresponding to the desired mode.