Abstract: A method for managing a queue of cells received from a plurality of sources, wherein the last cell received is stored at a receive address in a buffer, and a time stamp is established for the last cell received that represents the theoretical time it is to leave the queue. The receive address is inserted into a programmer at a location identified by the time stamp of the last cell received, and an occupancy bit associated with the time stamp is set to an active state. The first cell(s) to leave the queue from the first active occupancy bit following that of the cell that has just left the queue is determined, with the occupancy bits being classified in increasing order of the associated time stamps, and the occupancy bit of the first cell is set to an inactive state when it leaves the queue.

Abstract: In a method of routing cells in an asynchronous time-division multiplex switching network interconnecting input switches and output switches via switches, each input switch can be connected to each output switch via at least two paths. The transmission of a sequence of cells of a given call between one input switch, called the call input switch, and one output switch, called the call output switch, comprises the following steps:determining the set of N possible paths between the call input switch and the call output switch,setting up N sub-connections corresponding to the N possible paths,in the call input switch, systematically and equitably distributing the cells of the sequence to the N sub-connections, andin the call output switch, assembling the cells of the sequence to reconstitute the sequence.

Abstract: The invention relates to a switching network enabling a plurality of bothway I/O links to be interconnected. In one embodiment of the invention, the network includes at least two nodes, each node possessing not more than k incident I/O points, k.gtoreq.2, n sets of k extended I/O points, n.gtoreq.2, and extension/concentration devices enabling each of the k incident I/O points to be connected to one of the extended I/O points of each of the n sets. Each bothway I/O link is capable of being connected to one of the incident I/O points of one of the nodes, and each node is associated with a bothway switching matrix having k I/O ports. The nodes are interconnected in pairs by first and second one-way switching matrices each having k input ports and k output ports.