Patents by Inventor Patrick Gainer

Patrick Gainer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for storing and retrieving a translation of target program instruction from a host processor using fast look-up of indirect branch destination in a dynamic translation system
    Patent number: 7644210
    Abstract: Dynamic translation of indirect branch instructions of a target application by a host processor is enhanced by including a cache to provide access to the addresses of the most frequently used translations of a host computer, minimizing the need to access the translation buffer. Entries in the cache have a host instruction address and tags that may include a logical address of the instruction of the target application, the physical address of that instruction, the code segment limit to the instruction, and the context value of the host processor associated with that instruction. The cache may be a software cache apportioned by software from the main processor memory or a hardware cache separate from main memory.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: January 5, 2010
    Inventors: John Banning, Brett Coon, Linus Torvalds, Brian Choy, Malcolm Wing, Patrick Gainer
  • Fast look-up of indirect branch destination in a dynamic translation system
    Patent number: 7111096
    Abstract: Dynamic translation of indirect branch instructions of a target application by a host processor is enhanced by including a cache to provide access to the addresses of the most frequently used translations of a host computer, minimizing the need to access the translation buffer. Entries in the cache have a host instruction address and tags that may include a logical address of the instruction of the target application, the physical address of that instruction, the code segment limit to the instruction, and the context value of the host processor associated with that instruction. The cache may be a software cache apportioned by software from the main processor memory or a hardware cache separate from main memory.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: September 19, 2006
    Assignee: Transmeta Corporation
    Inventors: John Banning, Brett Coon, Linus Torvalds, Brian Choy, Malcolm Wing, Patrick Gainer
  • Fast look-up of indirect branch destination in a dynamic translation system
    Patent number: 6615300
    Abstract: Dynamic translation of indirect branch instructions of a target application by a host processor is enhanced by including a cache to provide access to the addresses of the most frequently used translations of a host computer, minimizing the need to access the translation buffer. Each entry in the cache includes a host instruction address, a logical address of the instruction of the target application, the physical address of that instruction, the code segment limit to the instruction, and the context value of the host processor associated with that instruction, the last four named components constituting tags to the host instruction address, and a valid-invalid bit. In a basic embodiment, the cache is a software cache apportioned by software from the main processor memory chips.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: September 2, 2003
    Assignee: Transmeta Corporation
    Inventors: John Banning, Brett Coon, Linus Torvalds, Brian Choy, Malcolm Wing, Patrick Gainer