Patents by Inventor Patrick J. Landy

Patrick J. Landy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020086651
    Abstract: An automatic gain control (AGC) amplifier including a high gain transimpedance amplifier, a resistive feedback network and multiple transconductance stages coupled in the feedback path of the AGC amplifier. The feedback network receives an input signal and is coupled to the output of the high gain amplifier and has multiple intermediate nodes. Each transconductance stage has an input coupled to an intermediate node of the feedback network and an output coupled to the input of the high gain amplifier. Each transconductance stage is independently controllable to position a virtual ground within the feedback network to control closed loop gain. Each transconductance stage may have a bias current input coupled to a bias current control circuit. The control circuit controls each bias current to vary the gain of the AGC amplifier. The bias currents may be linearly controlled employing a ramp function to achieve a linear in dB gain response.
    Type: Application
    Filed: December 21, 2001
    Publication date: July 4, 2002
    Inventors: John S. Prentice, Patrick J. Landy
  • Publication number: 20020080537
    Abstract: An electrostatic discharge (ESD) switch circuit for an integrated circuit (IC) with multiple power inputs for improving pin-to-power isolation of the IC. The IC includes a plurality of positive power pins and a corresponding plurality of negative power pins. The IC also includes an ESD ring network with a high ESD bus and a low ESD bus. The IC further includes a control circuit indicating one of several operational modes. The ESD switch circuit includes a first switch circuit that couples the high ESD bus to a first positive power pin in a first operational mode and that couples the high ESD bus to a second positive power pin in a second operational mode. The ESD switch circuit further includes a second switch circuit that couples the low ESD bus to a first negative power pin in the first operational mode and that couples the low ESD bus to a second negative power pin in the second operational mode.
    Type: Application
    Filed: December 21, 2000
    Publication date: June 27, 2002
    Inventor: Patrick J. Landy