Abstract: A differential switched capcitor filter section which includes a differential amplifier (OTA), a first set of switched capacitors (C11, C12) coupled between a non-inverting output (+) and an inverting input (-) of the differential amplifier (OTA), and a second set of switched capacitors (C21, C22) coupled between an inverting output (-) and a non-inverting input (+) of the differential amplifier (OTA). In the sets of switched capacitors (C11, C12; C21, C22), first terminals of the capacitors are coupled to a corresponding one of the outputs (+; -) of the differential amplifier (OTA) thru first switches (S1.11, S1.12; S1.21, S1.22), and to one of the differential inputs (Vin+; Vin-) of the filter section thru second switches (S2.11, S2.12; S2.21, S2.22). Second terminals of the capacitors are coupled to a corresponding one of the inputs (-, +) of the differential amplifier (OTA) thru third switches (S3.11, S3.12; S3.21, S3.22), and to a reference terminal thru fourth switches (S4.11, S4.12; S4.21, S4.22).

Abstract: An inverting delay circuit including a differential amplifier (OTA) having a non-inverting input (+) coupled to ground, an inverting input (-) and an output; an input capacitor (Cin) which is coupled between an input of the inverting delay circuit and the inverting input (-) during a first switching phase (.phi.), and which is discharged during a second switching phase (); a feedback capacitor (Cx) which is coupled between the output and the inverting input (-) of the differential amplifier (OTA) during the first switching phase (.phi.), and between the inverting input (-) and ground during the second switching phase (); and an output capacitor (Co) which is coupled between the output and the inverting input (-) during the second switching phase (), the output capacitor (Co) being discharged during the first switching phase (.phi.), a charge on the feedback capacitor (Cx) being transferred to the output capacitor (Co) during the second switching phase ().