Abstract: A DSP device is disclosed having multiple DMA controllers with global DMA access to all volatile memory resources in the DSP device. In a preferred embodiment, each of the DMA controllers is coupled to each of the memory buses and is configured to control each of the memory buses. A memory bus multiplexer may be coupled between the subsystem memory bus and each of the DMA controllers, and an arbiter may be used to set the memory bus multiplexer so as to allow any one of the DMA controllers to control the memory bus. The memory bus may also be controlled by the host port interface via the memory bus multiplexer. A round-robin arbitration technique is used to provide each of the controllers and the host port interface fair access to the memory bus. This approach may advantageously provide increased flexibility in the use of DMA controllers to transfer data from place to place, with only a minimal increase in complexity.

Abstract: A multiprocessor system includes a plurality of data processors. Each data processor includes: a data processing core; a memory forming a local portion of a unified memory; and a global memory arbitration logic. Each local portion of the unified memory is dual ported. The global memory arbitration logic arbitrates access to a first port among the corresponding data processing core and a close data processing core. The global memory arbitration logic arbitrates access to a second port of another data processor among data processing cores having a far connection to that local portion of unified memory. The dual port memory is preferably time multiplexed. The global memory arbitration logic grants a local peripheral bus priority access to both ports of the local portion of unified memory.

Abstract: In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. When a packet is received by a shared high level data link controller, the data signal groups are processed and placed in a temporary storage unit. The address signal group of the received packet is applied to channel block unit where the digital signal processor subsystem, to which the packet is directed, is identified and an INTERRUPT signal corresponding to the identified digital signal processor subsystem is generated. The INTERRUPT signal is applied to a switch. The switch, which receives the signal groups from the temporary storage unit, directs the signal groups to a buffer memory in the channel associated with the identified signal processing subsystem.

Abstract: In a digital processing unit having a plurality of digital signal processors, a first digital signal processor can request a direct transfer of a signal group stored in the memory unit of a second digital signal processor. In order to insure that the second digital signal is active, a control signal is generated by the direct memory access controller of the first digital signal processor. The control signal is applied the directly to the memory access controller of the second digital signal processor. When the second digital signal processor is in an IDLE mode, the control signal activates the second digital signal processor.

Abstract: A pole piece assembly (28) for an electric motor (20) formed of stacked interlocked lamina (46) that define a first set of stacked lamina (50) and a second set of stacked lamina (52). Each of the lamina (46) of the first (50) and second (52) sets of stacked lamina include a hole (60) with the holes (60) being aligned with each other to define an internal cavity. A post (64) is disposed within the cavity with the post (64) having an outer surface (66) and a pair of bores (68) disposed therein. The pole piece assembly (28) is characterized by each of the lamina (46) of the second set of stacked lamina (52) further including a notch (74, 78) with the notch (74, 78) mating with the hole (60). The notches (74, 78) of the second set of stacked lamina (52) are aligned with each other to define a passageway into the internal cavity with the bore (68) of the post (64) being aligned with the passageway to expose the bore (68).

Abstract: In order to sort signal group elements organized in blocks in a time-division multiplex protocol into frames of related elements, an address unit addresses the first element in each of the element blocks, then the second element in each element block, etc until all of the elements of all of the blocks have been addressed. In this manner, the related elements are sorted into frames of elements. The address unit performs this element sorting using a base address, an element index equal to the number of elements in a block, and a frame index equal to {the number of elements times (the number of frames minus one)} minus one as parameters.

Abstract: As the digital signal processor has become more flexible, the direct memory access controller has assumed greater computational power to permit the core processing unit to perform its specialized processing without responding to signal transfer requests. Not only does the direct memory access controller control the exchange of signal groups between the memory unit and the core processing unit, but the direct memory access controller is also responsible for the transfer of signal groups within the digital signal processor that originate from the serial port, and the interface unit (the unit that implements the direct transfer of signal groups from the memory unit of one digital signal processor to a second signal processor). The direct memory access controller has programmable channels that permit the signal group source component to be coupled to the signal group destination component. The address unit of the direct memory access unit must be able to accommodate a plurality of addressing modes.

Abstract: A multi-core DSP device includes a shared program memory to eliminate redundancy and thereby reduce the size and power consumption of the DSP device. Because each of the program cores typically executes the same software program, memory requirements may be reduced by having multiple processor cores share only a single copy of the software. Accordingly, a program memory couples to each of the processor cores by a corresponding instruction bus. Preferably the program memory services two or more instruction requests in each clock cycle. Data is preferably stored in separate memory arrays local to the processor core subsystems and accessible by the processor cores via a dedicated data bus. In one specific implementation, the program memory includes a wrapper that can perform one memory access in the first half of each clock cycle and a second memory access in the second half of each clock cycle.

Abstract: A pole piece assembly (28) for an electric motor (20) formed of stacked interlocked lamina (46) that define a first set of stacked lamina (50) and a second set of stacked lamina (52). Each of the lamina (46) of the first (50) and second (52) sets of stacked lamina include a hole (60) with the holes (60) being aligned with each other to define an internal cavity. A post (64) is disposed within the cavity with the post (64) having an outer surface (66) and a pair of bores (68) disposed therein. The pole piece assembly (28) is characterized by each of the lamina (46) of the second set of stacked lamina (52) further including a notch (74, 78) with the notch (74, 78) mating with the hole (60). The notches (74, 78) of the second set of stacked lamina (52) are aligned with each other to define a passageway into the internal cavity with the bore (68) of the post (64) being aligned with the passageway to expose the bore (68).

Abstract: In a digital signal processing unit, addressing apparatus implements a multiplicity of addressing modes. The addressing modes include a circular buffer memory mode, a frame mode, and a sorting mode. To increase the speed of the address modification, the index, the index in the presence of a positive wrap-around, and the index in the presence of negative wrap-around are determined together. Other apparatus determines the addressing mode and provides control signals for the selection of the correct index. The correct index is combined with the base address to provide the next new address.

Abstract: In digital signal processors serial data is passed in out and of the chip in a time division multiplexed (TDM) fashion. The TDM stream consists of many independent channels of serial data. The complexity of generating interleaved TDM serial data from multiple sources particularly in the case of multi-processor systems. This process is normally driven by a program resident on each processor. The proper sequencing of the TDM serial stream must be tested prior to making the multi-processor device ready for its application. This invention describes the use of minimal added hardware and a single output pin allowing the test and debug of program errors or device malfunctions in output serial data.

Abstract: A method and system for optimizing a mobile radio network topology for an N node network where each node has K connecting links. A base network topology is established and a cost value is determined for the base network. It is determined if all possible local transformations on the base network topology have been performed and if not a local transformation is performed on the base network to form a transformed network. A cost is calculated for the transformed network and the cost is compared with the cost of a base network. The transformed network is established as the base network if the cost of the transformed network is less than the cost of the base network.

Abstract: In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. When a packet is received by a shared high level data link controller, the data signal groups are processed and placed in a temporary storage unit. The address signal group of the received packet is applied to channel block unit where the digital signal processor subsystem, to which the packet is directed, is identified and an INTERRUPT signal corresponding to the identified digital signal processor subsystem is generated. The INTERRUPT signal is applied to a switch. The switch, which receives the signal groups from the temporary storage unit, directs the signal groups to a buffer memory in the channel associated with the identified signal processing subsystem.

Abstract: In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. Using a first interrupt signal after each transfer of signal groups from the peripheral direct memory access unit, the data can be efficiently transferred from a channel memory of the peripheral direct memory access unit to the high level data link controller. A second interrupt from the high level data link controller when a last word of a packet is transferred thereto causes a new channel memory to be accessed.

Abstract: In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the high level data link controller is shared by the subsystems. Using a first interrupt signal after each transfer of signal groups from the peripheral direct memory access unit, the data can be efficiently transferred from a channel memory of the peripheral direct memory access unit to the high level data link controller. A second interrupt from the high level data link controller when a last word of a packet is transferred thereto causes a new channel memory to be accessed. An abort signal is generated when a signal group for a packet being processed by the high level data link controller is not available in a timely manner.

Abstract: A slave interface unit controls the exchange of data between a master processing unit and a plurality of slave processing units operating in the asynchronous transfer mode (ATM) of operation. The ATM slave interface unit has a receive unit and a transmit unit that exchange data cells and control signals with the ATM master processing unit. The receive unit and the transmit unit are coupled to a receive buffer storage unit and a transmit buffer storage unit, respectively. The receive buffer storage unit and the transmit buffer storage unit exchange data and control signals with the direct memory access unit. The ATM slave interface unit includes a configuration interface unit having a register that identifies the location in the data cell where the destination address is located and relates the destination address to the particular processing unit or memory location. The receive buffer unit uses the information in the register to determine the destination of the data cell.

Abstract: A multiprocessor system includes a plurality of data processors. Each data processor includes: a data processing core; a memory forming a local portion of a unified memory; and a global memory arbitration logic. Each local portion of the unified memory is dual ported. The global memory arbitration logic arbitrates access to a first port among the corresponding data processing core and a close data processing core. The global memory arbitration logic arbitrates access to a second port of another data processor among data processing cores having a far connection to that local portion of unified memory. The dual port memory is preferably time multiplexed. The global memory arbitration logic grants a local peripheral bus priority access to both ports of the local portion of unified memory.

Abstract: A DSP device is disclosed having multiple DMA controllers with global DMA access to all volatile memory resources in the DSP device. In a preferred embodiment, each of the DMA controllers is coupled to each of the memory buses and is configured to control each of the memory buses. A memory bus multiplexer may be coupled between the subsystem memory bus and each of the DMA controllers, and an arbiter may be used to set the memory bus multiplexer so as to allow any one of the DMA controllers to control the memory bus. The memory bus may also be controlled by the host port interface via the memory bus multiplexer. A round-robin arbitration technique is used to provide each of the controllers and the host port interface fair access to the memory bus. This approach may advantageously provide increased flexibility in the use of DMA controllers to transfer data from place to place, with only a minimal increase in complexity.

Abstract: A multi-core DSP device includes a shared program memory to eliminate redundancy and thereby reduce the size and power consumption of the DSP device. Because each of the program cores typically executes the same software program, memory requirements may be reduced by having multiple processor cores share only a single copy of the software. Accordingly, a program memory couples to each of the processor cores by a corresponding instruction bus. Preferably the program memory services two or more instruction requests in each clock cycle. Data is preferably stored in separate memory arrays local to the processor core subsystems and accessible by the processor cores via a dedicated data bus. In one specific implementation, the program memory includes a wrapper that can perform one memory access in the first half of each clock cycle and a second memory access in the second half of each clock cycle.

Abstract: Users or subscribers of a spread spectrum synchronous communications system provide signals to the central station or base unit of that system, and receive signals therefrom. Proper synchronization among those users (and their signals) is needed to ensure proper operation of the system. To ensure proper synchronization among those users, the signal produced by each user is checked for presence and amount of any offset error. This is accomplished by using three despreaders for the signal for each user. For one such user, each such despreader for that user receives the spreading code for that user. However, the spreading code as received by any one such despreader is time-delayed with respect to the spreading code as received by the other two despreaders. Each such despreader receives the spreading code with a different amount of delay imposed on that spreading code. The outputs of the three despreaders are digitally combined (e.g. compared), or compared, to produce the offset estimate for that user.