Abstract: A data packet transmission system is disclosed. The system comprises a processor (178) having a memory block (202) and a communication controller (204). The processor (178) stores a data packet (205), a buffer descriptor array (206), and a header (208) in the memory block (202). The buffer descriptor array (206) has a first plurality of elements (206b, 206d, 206f, 206h, 206i), each indicating a respective segment (205a-205e) of the data packet (206), and a second plurality of elements (206a, 206c, 206e, 206g), each indicating the header (208). The processor (178) supplies the location of the buffer descriptor array (206) to the communication controller (204). In response, the communication controller (204) transmits a plurality of cells (222, 224, 226, 228), each cell including the header (208) and a segment of the data packet (205), to a destination system (180).

Abstract: A method for simulating the behavior of a metastable state machine is presented. The method includes outputting a transitional value when the state machine exhibits metastable behavior, such as when a set-up or hold violation occurs. A randomly-determined value is output after the transitional value is output for a predetermined period of time.

Abstract: A digital demodulator or receiver (22) having an interface (24) for receiving an input signal modulated with digital data, a multiplier (36) for multiplying the input signal with a local oscillator signal (LO) to generate a product signal, and an integrator (38) for periodically integrating the product signal to generate a sequence of integrated signals, each having an amplitude indicative of a respective portion of the digital data, additionally includes a circuit (30, 32) for directly generating a plurality of logic signals and a summer (34) for summing the logic signals to directly synthesize the local oscillator signal (LO). The local oscillator signal (LO) thereby produced has a fundamental component and third and fourth harmonic components and is shaped to ensure that each of the third and fourth harmonic components has an amplitude substantially less than that of the fundamental component.

Abstract: A digital demodulator or receiver (22) having an interface (24) for receiving an input signal modulated with digital data, a multiplier (26) for multiplying the input signal with a local oscillator signal (LOa-LOd) to generate a product signal, and an integrator (38) for periodically integrating the product signal to generate a sequence of integrated signals, each having an amplitude indicative of a respective portion of the digital data, operates in a SEARCH mode to supply acquisition reference signals (1xi, 1xq, 2xi, 2xq) to the multipliers (36). The resulting integrated values (Ia-Id) are proportional to the sine and cosine of the pahse (.phi.) of the input signal. The polarities (Sa-Sd) of these integrated values (Ia-Id) are processed to estimate this phase (.phi.) and to generate a reset signal (RESYNC) for the receiver (22) at the appropriate time.

Abstract: A digital demodulator (10) operates by multiplying an input signal with first and second orthogonal demodulation reference signals (Loa, LOb) to generate respective product signals, which are then integrated to generate first and second integrated values (a, b) indicative of digital data encoded in the input signal. These integrated values (a, b) are digitized to generate first and second digital values (a, b). A first error signal a-a) indicative of the difference between the first integrated value (a) and the first digital value (a) is generated, and the first error signal (a-a) is combined with the second digital value (b) to generate a first feedback signal. This first feedback signal is utilized to generate a control signal (ab-ba) indicative of phase difference between the input signal and the demodulation reference signals (LOa, LOb).

Abstract: A first-in-first out (FIFO) register 100 for storage of up to two-bytes of data is operable by two control units 10, 20 for simultaneous read and write operations with no wait states. The FIFO register 100 comprises a first register 101, a second register 102 and a controller U35. The first register 101 may be multplexed between the two control units 10, 20 for write operations by either unit. The second register 102 is in communication with the first register 101 and may be read by either control unit 10, 20. Data is transferred from the first register 101 to the second register 102 under the direction of the controller U35 such that data may be read by one control unit 10, 20 while data is being simultaneously written by the other control unit 10, 20.

Abstract: A binary transversal filter (200) in which the delay line of flip-flops (A-L, A'-L') is driven by timing signals (CLK, CLK*, CLKD, CLKD*) that are the same clock rate as the clock rate (CLK) of the encoded binary signals (IMPULSE 0, IMPULSE 1) being introduced into the delay line forming the binary transversal filters (200). The timing signal (CLK, CLK*, CLKD, CLKD*) that time or clock the stages of the delay line (A-L, A'-L') are phases of the clock (CLK) that introduces the encoded binary signals (IMPULSE 0, IMPULSE 1) into the delay line (A-L, A'-L'). Two substantially identical binary transversal filters (200a, 200b) are used to convert two encoded binary data streams (IMPULSE 0, IMPULSE 1) into a duobinary signal. The output of the two binary transversal filters (200a, 200b) are summed (Q2) and passed to a programmable amplifier (210), the gain of which is turned on when there is data in the encoded binary signals (IMPULSE 0, IMPULSE 1) to be converted and transmitted and is turned off otherwise.