Abstract: Methods and apparatus are provided for efficiently normalizing and denormalizing data for cryptography processing. The normalization and denormalization techniques can be applied in the context of a cryptography accelerator coupled with a processor. Hardware normalization techniques are applied to data prior to cryptography processing. Context circuitry tracks the shift amount used for normalization. After cryptography processing, the processed data is denormalized using the shift amount tracked by the context circuitry.

Abstract: Aspects of the invention for converting interlace formatted video to progressive scan video, may include a color edge detector block (306) adapted to determined edges in interlaced formatted video. A threshold and gain processor block (308) coupled to the color edge detector block (306) may be adapted to quantify a likelihood of motion for each pixel comprising at least a portion of the interlaced scanned video using a motion value. A binder block (310) coupled to the threshold and gain processor block (308) may be configured to combine the motion value for each component of a luminance and chrominance of each of the pixels. A resampler block (314) may be coupled to the binder to determine an actual pixel value. The resampler block (314) may include at least one of a vertical and a horizontal filter adapted to determine an actual value of each of the pixels in at least a portion of the interlaced scanned video.

Abstract: A system and method that produces a spatial average for interlaced video in a deinterlacer. The system detects edges in the video images and determines the angle at which the edges are oriented based on the gradient in the x-direction and the gradient in the y-direction. The direction of the edge is determined using the angle information of the edge. The system may also determine the strength of the edge. Based on the determined characteristics of the edge a filter may be selected to produce a spatial average of the edge in the image.

Abstract: A system and method that determines the direction of an edge in a video image using a gradient of the edge in a first direction and a gradient of the edge in a second direction. The system uses the sign of the product of the gradient in the first direction and the gradient in the second direction along with a ratio of multiples of the two gradients to determine the direction of the edge. The direction may correspond to an angle range, where the ratio of the gradients corresponds to a trigonometric function of the angle of the edge.

Abstract: A system and method that determines the strength of an edge in a video image using a gradient of the edge in a first direction and a gradient of the edge in a second direction. The system uses the gradient in the first direction and the gradient in the second direction to approximate a distance function to determine the strength of the edge. A programmable threshold may be used in the determination, where an edge is treated like it does not exist if the distance is less than the threshold. The distance function may be an approximation of the Cartesian distance function.

Abstract: A system and method that abstracts an interrupt from a group of interrupts, which may occur in a module, to call another module. Abstracting one interrupt from a group of interrupts allows the called module to deal with only one interrupt. The choice of the interrupt may be based on the configuration of the module from which the interrupts are originated. In an embodiment of the present invention, the abstracted interrupt triggers an event. When the triggered event is completed, an interrupt may be fired off to the target module. An interrupt handler in the target module or an external interrupt handler may handle the interrupt that calls the target module.

Abstract: The present invention relates to electronic information access systems, methods of creation and related commercial models. Additionally, a mouse over navigation interface is provided for user selectable viewing of a desired display.

Abstract: Systems and methods for filtering to comply with copy-protection regulations set forth for HDTV signals by the MPAA are presented. A copy-protection filter constrains the resolution of the HDTV signal when copy-protection bits are present in a video signal. The copy-protection filter may be placed in an analog data stream before the video signal is converted from a digital to an analog signal. A second copy-protection filter is optionally placed in a digital data stream. The copy-protection filter may be combined with other filters in a video encoder, or with a scaler before the input video data stream enters a compositor.

Abstract: A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Abstract: Aspects of the invention include a 3:2 pull down detector coupled to a 3:2 cadence processor and a color edge detector coupled to a binder. The binder may be coupled to a 3:2 cadence processor. A filter, which may be a temporal or infinite impulse response filter, may be coupled to the binder. A selector may also be coupled to the 3:2 cadence processor. A memory and a processor may also be coupled to any of the 3:2 pull down detector, the 3:2 cadence processor, the color edge detector, the binder, the filter and said output selector. The selector may select between a filtered deinterlaced output and a reverse 3:2 pull down output.

Abstract: Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a plurality of possible display pipelines and that performs at least a first processing step on received data. A buffer stores the processed data and a second display pipeline that is formed in real time from a plurality of possible display pipelines performs at least a second processing step on stored data.

Abstract: Aspects of the invention for converting interlace formatted video to progressive scan video, may include a color edge detector block (306) adapted to determined edges in interlaced formatted video. A threshold and gain processor block (308) coupled to the color edge detector block (306) may be adapted to quantify a likelihood of motion for each pixel comprising at least a portion of the interlaced scanned video using a motion value. A binder block (310) coupled to the threshold and gain processor block (308) may be configured to combine the motion value for each component of a luminance and chrominance of each of the pixels. A resampler block (314) may be coupled to the binder to determine an actual pixel value. The resampler block (314) may include at least one of a vertical and a horizontal filter adapted to determine an actual value of each of the pixels in at least a portion of the interlaced scanned video.

Abstract: Systems and methods are disclosed for hardware assisted format changes in a display controller. One embodiment of the invention relates to a format change system comprising a register DMA controller and a register update list. The register update list contains at least one instruction. The register DMA controller is adapted to obtain and use at least one instruction to configure at least one display pipeline from a plurality of display pipelines in response to at least one trigger event.

Abstract: Systems and methods are disclosed for filter modules in a video display system or network. One embodiment relates to a method for operating a filter module in a video display network comprising determining a picture type, display type and operation of the display network. The method further comprises determining, in real time, a filter configuration from a plurality of possible filter configurations based on the determined picture type, display type and operation.

Abstract: Systems and methods are disclosed for video processing modules. More specifically a network is disclosed for processing data. The network comprises a register DMA controller adapted to support register access and at least one node adapted to the data. At least one link communicates with the node, and is adapted to transmit data and at least one network module communicates with at least the link, and is adapted to route data to at least the link.

Abstract: Systems and methods are disclosed for a bus, link or interface. More specifically, systems and methods are discloses for a bus, link or interface adapted to transmit data and control information to at least one processing module and provide synchronization between the data and the control information without requiring the transmission of blank pixels or timing information.

Abstract: Methods and apparatus are provided for generating interrupts associated with the completion of data processing. An external host may pass a first data block to a first processing engine and later pass a second data block to a second processing engine. In typical implementations, the external host expects that processing of the first data block completes first. To prevent errors and faults on the part of the external host, an interrupt associated with the processing of the second data block completing first is collapsed onto the first data block.

Abstract: Provided is an architecture for a cryptography accelerator chip that allows significant performance improvements over previous prior art designs. In various embodiments, the architecture enables parallel processing of packets through a plurality of cryptography engines and includes a classification engine configured to efficiently process encryption/decryption of data packets. Cryptography acceleration chips in accordance may be incorporated on network line cards or service modules and used in applications as diverse as connecting a single computer to a WAN, to large corporate networks, to networks servicing wide geographic areas (e.g., cities). The present invention provides improved performance over the prior art designs, with much reduced local memory requirements, in some cases requiring no additional external memory. In some embodiments, the present invention enables sustained full duplex Gigabit rate security processing of IPSec protocol data packets.

Abstract: Provided is an architecture for a cryptography accelerator chip that allows significant performance improvements over previous prior art designs. In various embodiments, the architecture enables parallel processing of packets through a plurality of cryptography engines and includes a classification engine configured to efficiently process encryption/decryption of data packets. Cryptography acceleration chips in accordance may be incorporated on network line cards or service modules and used in applications as diverse as connecting a single computer to a WAN, to large corporate networks, to networks servicing wide geographic areas (e.g., cities). The present invention provides improved performance over the prior art designs, with much reduced local memory requirements, in some cases requiring no additional external memory. In some embodiments, the present invention enables sustained full duplex Gigabit rate security processing of IPSec protocol data packets.

Abstract: Methods and apparatus are provided for efficiently normalizing and denormalizing data for cryptography processing. The normalization and denormalization techniques can be applied in the context of a cryptography accelerator coupled with a processor. Hardware normalization techniques are applied to data prior to cryptography processing. Context circuitry tracks the shift amount used for normalization. After cryptography processing, the processed data is denormalized using the shift amount tracked by the context circuitry.