Patents by Inventor Patrick M. Paluda

Patrick M. Paluda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wirebond structure and method to connect to a microelectronic die
    Patent number: 7855103
    Abstract: A wirebond structure includes a copper pad formed on or in a surface of a microelectronic die. A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable contact between the bond wire and the copper pad in at least one of an oxidizing environment and an environment with temperatures up to at least about 350° C.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: December 21, 2010
    Assignee: Intel Corporation
    Inventors: Robert J. Gleixner, Donald Danielson, Patrick M. Paluda, Rajan Naik
  • WIREBOND STRUCTURE AND METHOD TO CONNECT TO A MICROELECTRONIC DIE
    Publication number: 20080227285
    Abstract: A wirebond structure includes a copper pad formed on or in a surface of a microelectronic die. A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable contact between the bond wire and the copper pad in at least one of an oxidizing environment and an environment with temperatures up to at least about 350° C.
    Type: Application
    Filed: May 27, 2008
    Publication date: September 18, 2008
    Inventors: ROBERT J. GLEIXNER, DONALD DANIELSON, PATRICK M. PALUDA, RAJAN NAIK
  • Wirebond structure and method to connect to a microelectronic die
    Patent number: 7393772
    Abstract: A wirebond structure includes a copper pad formed on or in a surface of a microelectronic die. A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable contact between the bond wire and the copper pad in at least one of an oxidizing environment and an environment with temperatures up to at least about 350° C.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: July 1, 2008
    Assignee: Intel Corporation
    Inventors: Robert J. Gleixner, Donald Danielson, Patrick M. Paluda, Rajan Naik
  • Wirebond structure and method to connect to a microelectronic die
    Patent number: 6924554
    Abstract: A wirebond structure includes a copper pad formed on or in a surface of a microelectronic die. A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable contact between the bond wire and the copper pad in at least one of an oxidizing environment and an environment with temperatures up to at least about 350° C.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: August 2, 2005
    Assignee: Intel Corporation
    Inventors: Robert J. Gleixner, Donald Danielson, Patrick M. Paluda, Rajan Naik
  • Protecting delicate semiconductor features during wet etching
    Publication number: 20040072448
    Abstract: A wet etching solution may be utilized to remove insulator material between delicate structures. Surface tension effects of the wet etching solution may tend to collapse or deform delicate features. By applying sonic energy during the wet etch process and/or the removal of the wafer from a wet etching bath, the adverse effects of surface tension may be counteracted.
    Type: Application
    Filed: October 15, 2002
    Publication date: April 15, 2004
    Inventors: Justin K. Brask, Vijayakumar S. Ramachandrarao, Kevin P. O'Brien, Patrick M. Paluda
  • Wirebond structure and method to connect to a microelectronic die
    Patent number: 6683383
    Abstract: A wirebond structure includes a copper pad formed on or in a surface of a microelectronic die. A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable contact between the bond wire and the copper pad in at least one of an oxidizing environment and an environment with temperatures up to at least about 350° C.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: January 27, 2004
    Assignee: Intel Corporation
    Inventors: Robert J. Gleixner, Donald Danielson, Patrick M. Paluda, Rajan Naik
  • Wirebond structure and method to connect to a microelectronic die
    Publication number: 20030205827
    Abstract: A wirebond structure includes a copper pad formed on or in a surface of a microelectronic die. A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable contact between the bond wire and the copper pad in at least one of an oxidizing environment and an environment with temperatures up to at least about 350° C.
    Type: Application
    Filed: June 5, 2003
    Publication date: November 6, 2003
    Applicant: Intel Corporation
    Inventors: Robert J. Gleixner, Donald Danielson, Patrick M. Paluda, Rajan Naik
  • Wirebond structure and method to connect to a microelectronic die
    Publication number: 20030075804
    Abstract: A wirebond structure includes a copper pad formed on or in a surface of a microelectronic die. A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable contact between the bond wire and the copper pad in at least one of an oxidizing environment and an environment with temperatures up to at least about 350° C.
    Type: Application
    Filed: October 18, 2001
    Publication date: April 24, 2003
    Applicant: Intel Corporation
    Inventors: Robert J. Gleixner, Donald Danielson, Patrick M. Paluda, Rajan Naik